39 lines
724 B
Systemverilog
39 lines
724 B
Systemverilog
`include "rv32.sv"
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module top (
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input clk,
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/* serial flash */
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output flash_clk,
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output flash_csn,
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inout flash_io0,
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inout flash_io1,
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/* LEDs */
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output [7:0] leds,
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/* UART */
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input uart_rx,
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output uart_tx
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);
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logic flash_io0_en;
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logic flash_io0_in;
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logic flash_io0_out;
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logic flash_io1_en;
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logic flash_io1_in;
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logic flash_io1_out;
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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) flash_io [1:0] (
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.PACKAGE_PIN({flash_io1, flash_io0}),
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.OUTPUT_ENABLE({flash_io1_en, flash_io0_en}),
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.D_IN_0({flash_io1_in, flash_io0_in}),
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.D_OUT_0({flash_io1_out, flash_io0_out})
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);
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rv32 rv32 (
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.clk(clk)
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);
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endmodule
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