19 lines
286 B
Systemverilog
19 lines
286 B
Systemverilog
`ifndef SYNC
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`define SYNC
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module sync #(
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parameter BITS = 1
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) (
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input clk,
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input [BITS-1:0] in,
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output [BITS-1:0] out
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);
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logic [BITS-1:0] metastable;
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always_ff @(posedge clk) begin
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metastable <= in;
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out <= metastable;
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end
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endmodule
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`endif
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