43 lines
843 B
Systemverilog
43 lines
843 B
Systemverilog
`ifndef RV32_FETCH
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`define RV32_FETCH
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`include "rv32_opcodes.sv"
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module rv32_fetch (
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input clk,
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/* control in (from hazard) */
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input stall_in,
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input flush_in,
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/* control in (from mem) */
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input branch_taken_in,
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/* data in (from mem) */
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input [31:0] branch_pc_in,
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/* data out */
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output [31:0] pc_out,
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output [31:0] instr_out
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);
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logic [31:0] instr_mem [255:0];
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logic [31:0] next_pc;
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logic [31:0] pc = branch_taken_in ? branch_pc_in : next_pc;
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initial
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$readmemh("progmem_syn.hex", instr_mem);
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always_ff @(posedge clk) begin
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if (!stall_in) begin
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instr_out <= instr_mem[pc[31:2]];
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next_pc <= pc + 4;
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pc_out <= pc;
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if (flush_in)
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instr_out <= RV32_INSTR_NOP;
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end
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end
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endmodule
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`endif
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