32 lines
589 B
Systemverilog
32 lines
589 B
Systemverilog
`ifndef RV32_MEM
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`define RV32_MEM
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module rv32_mem (
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input clk,
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/* control in */
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input read_en_in,
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input write_en_in,
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/* data in */
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input [31:0] result_in,
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input [31:0] rs2_value_in,
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/* data out */
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output [31:0] result_out,
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output [31:0] read_value_out
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);
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logic [31:0] data_mem [255:0];
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always @(posedge clk) begin
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result_out <= result_in;
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if (read_en_in)
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read_value_out <= data_mem[result_in[31:2]];
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if (write_en_in)
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data_mem[result_in[31:2]] <= rs2_value_in;
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end
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endmodule
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`endif
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