68 lines
2.1 KiB
Systemverilog
68 lines
2.1 KiB
Systemverilog
`ifndef RV32_HAZARD
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`define RV32_HAZARD
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module rv32_hazard_unit (
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/* control in */
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input [4:0] decode_rs1_unreg_in,
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input decode_rs1_read_unreg_in,
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input [4:0] decode_rs2_unreg_in,
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input decode_rs2_read_unreg_in,
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input decode_mem_fence_unreg_in,
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input decode_mem_read_in,
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input decode_mem_fence_in,
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input [4:0] decode_rd_in,
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input decode_rd_write_in,
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input execute_mem_fence_in,
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input mem_branch_mispredicted_in,
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input instr_read_in,
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input instr_ready_in,
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input data_read_in,
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input data_write_in,
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input data_ready_in,
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/* control out */
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output logic fetch_stall_out,
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output logic fetch_flush_out,
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output logic decode_stall_out,
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output logic decode_flush_out,
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output logic execute_stall_out,
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output logic execute_flush_out,
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output logic mem_stall_out,
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output logic mem_flush_out
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);
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logic rs1_matches;
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logic rs2_matches;
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logic fetch_wait_for_bus;
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logic fetch_wait_for_mem_read;
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logic fetch_wait_for_mem_fence;
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logic mem_wait_for_bus;
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assign rs1_matches = decode_rs1_unreg_in == decode_rd_in && decode_rs1_read_unreg_in;
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assign rs2_matches = decode_rs2_unreg_in == decode_rd_in && decode_rs2_read_unreg_in;
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assign fetch_wait_for_bus = instr_read_in && !instr_ready_in;
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assign fetch_wait_for_mem_read = (rs1_matches || rs2_matches) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
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assign fetch_wait_for_mem_fence = decode_mem_fence_unreg_in || decode_mem_fence_in || execute_mem_fence_in;
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assign mem_wait_for_bus = (data_read_in || data_write_in) && !data_ready_in;
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assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read || fetch_wait_for_bus;
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assign fetch_flush_out = 0;
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assign decode_stall_out = execute_stall_out;
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assign decode_flush_out = fetch_stall_out || mem_branch_mispredicted_in;
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assign execute_stall_out = mem_stall_out;
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assign execute_flush_out = decode_stall_out || mem_branch_mispredicted_in;
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assign mem_stall_out = mem_wait_for_bus;
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assign mem_flush_out = execute_stall_out;
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endmodule
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`endif
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