6d638404f1
This implementation uses a simpler state machine than the previous version. The receiver still needs to be implemented.
97 lines
2.3 KiB
Systemverilog
97 lines
2.3 KiB
Systemverilog
`ifndef UART
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`define UART
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localparam UART_REG_CLK_DIV = 2'b00;
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localparam UART_REG_STATUS = 2'b01;
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localparam UART_REG_DATA = 2'b10;
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module uart (
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input clk,
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input reset,
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/* serial port */
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input rx_in,
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output tx_out,
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/* control in */
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input sel_in,
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input read_in,
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input [3:0] write_mask_in,
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/* data in */
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input [31:0] address_in,
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input [31:0] write_value_in,
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/* data out */
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output [31:0] read_value_out
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);
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logic [15:0] clk_div;
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logic [15:0] tx_clks;
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logic [3:0] tx_bits;
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logic [9:0] tx_buf;
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initial
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tx_buf[0] = 1;
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assign tx_out = tx_buf[0];
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always_comb begin
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if (sel_in) begin
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case (address_in[3:2])
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UART_REG_CLK_DIV: begin
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read_value_out = {16'b0, clk_div};
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end
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UART_REG_STATUS: begin
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read_value_out = {31'b0, |tx_bits};
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end
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UART_REG_DATA: begin
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read_value_out = 0;
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end
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default: begin
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read_value_out = 32'bx;
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end
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endcase
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end else begin
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read_value_out = 0;
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end
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end
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always_ff @(posedge clk) begin
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if (sel_in) begin
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case (address_in[3:2])
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UART_REG_CLK_DIV: begin
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if (write_mask_in[1])
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clk_div[15:8] <= write_value_in[15:8];
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if (write_mask_in[0])
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clk_div[7:0] <= write_value_in[7:0];
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end
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UART_REG_DATA: begin
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if (write_mask_in[0] && !tx_bits) begin
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tx_clks <= clk_div;
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tx_bits <= 10;
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tx_buf <= {1'b1, write_value_in[7:0], 1'b0};
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end
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end
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endcase
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end
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if (tx_bits) begin
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if (tx_clks) begin
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tx_clks <= tx_clks - 1;
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end else begin
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tx_clks <= clk_div;
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tx_bits <= tx_bits - 1;
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tx_buf <= {1'b1, tx_buf[9:1]};
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end
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end
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if (reset) begin
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tx_bits <= 0;
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tx_buf[0] <= 1;
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end
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end
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endmodule
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`endif
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