63 lines
1.9 KiB
Systemverilog
63 lines
1.9 KiB
Systemverilog
`ifndef BUS_ARBITER
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`define BUS_ARBITER
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module bus_arbiter (
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/* instruction memory bus */
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input [31:0] instr_address_in,
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input instr_read_in,
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output logic [31:0] instr_read_value_out,
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output logic instr_ready,
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/* data memory bus */
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input [31:0] data_address_in,
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input data_read_in,
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input data_write_in,
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output logic [31:0] data_read_value_out,
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input [3:0] data_write_mask_in,
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input [31:0] data_write_value_in,
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output logic data_ready,
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/* common memory bus */
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output logic [31:0] address_out,
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output logic read_out,
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output logic write_out,
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input [31:0] read_value_in,
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output logic [3:0] write_mask_out,
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output logic [31:0] write_value_out
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);
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always_comb begin
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if (data_read_in || data_write_in) begin
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address_out = data_address_in;
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read_out = data_read_in;
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write_out = data_write_in;
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instr_read_value_out = 32'bx;
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data_read_value_out = read_value_in;
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write_mask_out = data_write_mask_in;
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write_value_out = data_write_value_in;
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instr_ready = 1'b0;
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data_ready = 1'b1;
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end else if (instr_read_in) begin
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address_out = instr_address_in;
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read_out = instr_read_in;
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write_out = 1'b0;
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instr_read_value_out = read_value_in;
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data_read_value_out = 32'bx;
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write_mask_out = 4'b0;
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write_value_out = 32'bx;
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instr_ready = 1'b1;
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data_ready = 1'b0;
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end else begin
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address_out = 32'bx;
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read_out = 1'b0;
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write_out = 1'b0;
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instr_read_value_out = 32'bx;
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data_read_value_out = 32'bx;
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write_mask_out = 4'b0;
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write_value_out = 32'bx;
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instr_ready = 1'b0;
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data_ready = 1'b0;
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end
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end
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endmodule
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`endif
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