8024a6075f
This reduces the amount of logic required and should speed the processor up slightly, as the critical path had moved from the execute stage to the branching logic in the mem/fetch stages.
53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
`ifndef RV32_BRANCH
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`define RV32_BRANCH
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`define RV32_BRANCH_OP_NEVER 2'b00
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`define RV32_BRANCH_OP_ZERO 2'b01
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`define RV32_BRANCH_OP_NON_ZERO 2'b10
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`define RV32_BRANCH_OP_ALWAYS 2'b11
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`define RV32_BRANCH_PC_SRC_IMM 1'b0
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`define RV32_BRANCH_PC_SRC_REG 1'b1
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module rv32_branch_pc_mux (
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/* control in */
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input pc_src_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] imm_value_in,
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/* data out */
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output logic [31:0] pc_out
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);
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logic [31:0] pc;
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assign pc = (pc_src_in ? rs1_value_in : pc_in) + imm_value_in;
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assign pc_out = {pc[31:1], 1'b0};
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endmodule
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module rv32_branch_unit (
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/* control in */
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input predicted_taken_in,
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input alu_non_zero_in,
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input [1:0] op_in,
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/* control out */
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output logic mispredicted_out
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);
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logic taken;
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always_comb begin
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case (op_in)
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`RV32_BRANCH_OP_NEVER: taken = 0;
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`RV32_BRANCH_OP_ZERO: taken = ~alu_non_zero_in;
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`RV32_BRANCH_OP_NON_ZERO: taken = alu_non_zero_in;
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`RV32_BRANCH_OP_ALWAYS: taken = 1;
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endcase
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end
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assign mispredicted_out = taken != predicted_taken_in;
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endmodule
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`endif
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