276688f9ef
This reduces the amount of logic slightly, and also removes the one cycle delay between a CSR read and a subsequent instruction reading from the destination register.
539 lines
19 KiB
Systemverilog
539 lines
19 KiB
Systemverilog
`ifndef RV32_CONTROL
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`define RV32_CONTROL
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`include "rv32_alu.sv"
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`include "rv32_csrs.sv"
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`include "rv32_branch.sv"
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`include "rv32_imm.sv"
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`include "rv32_mem.sv"
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`include "rv32_opcodes.sv"
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module rv32_control_unit (
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/* data in */
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input [31:0] instr_in,
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/* control in */
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input [4:0] rs1_in,
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input [4:0] rd_in,
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/* control out */
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output logic valid_out,
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output logic rs1_read_out,
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output logic rs2_read_out,
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output logic [2:0] imm_out,
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output logic [2:0] alu_op_out,
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output logic alu_sub_sra_out,
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output logic [1:0] alu_src1_out,
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output logic [1:0] alu_src2_out,
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output logic mem_read_out,
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output logic mem_write_out,
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output logic [1:0] mem_width_out,
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output logic mem_zero_extend_out,
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output logic mem_fence_out,
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output logic csr_read_out,
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output logic csr_write_out,
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output logic [1:0] csr_write_op_out,
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output logic csr_src_out,
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output logic [1:0] branch_op_out,
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output logic branch_pc_src_out,
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output logic rd_write_out
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);
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always_comb begin
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valid_out = 0;
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rs1_read_out = 0;
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rs2_read_out = 0;
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imm_out = 3'bx;
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alu_op_out = 3'bx;
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alu_sub_sra_out = 1'bx;
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alu_src1_out = 2'bx;
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alu_src2_out = 2'bx;
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mem_read_out = 0;
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mem_write_out = 0;
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mem_width_out = 2'bx;
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mem_zero_extend_out = 1'bx;
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mem_fence_out = 0;
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csr_read_out = 0;
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csr_write_out = 0;
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csr_write_op_out = 2'bx;
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csr_src_out = 1'bx;
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branch_op_out = `RV32_BRANCH_OP_NEVER;
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branch_pc_src_out = 1'bx;
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rd_write_out = 0;
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casez (instr_in)
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`RV32_INSTR_LUI: begin
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valid_out = 1;
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imm_out = `RV32_IMM_U;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_ZERO;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_AUIPC: begin
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valid_out = 1;
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imm_out = `RV32_IMM_U;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_PC;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_JAL: begin
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valid_out = 1;
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imm_out = `RV32_IMM_J;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_PC;
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alu_src2_out = `RV32_ALU_SRC2_FOUR;
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branch_op_out = `RV32_BRANCH_OP_ALWAYS;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_JALR: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_PC;
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alu_src2_out = `RV32_ALU_SRC2_FOUR;
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branch_op_out = `RV32_BRANCH_OP_ALWAYS;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_REG;
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rd_write_out = 1;
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end
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`RV32_INSTR_BEQ: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_BNE: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_BLT: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_SLT;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_BGE: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_SLT;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_BLTU: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_SLTU;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_BGEU: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_B;
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alu_op_out = `RV32_ALU_OP_SLTU;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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branch_op_out = `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out = `RV32_BRANCH_PC_SRC_IMM;
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end
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`RV32_INSTR_LB: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_read_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_BYTE;
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mem_zero_extend_out = 0;
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rd_write_out = 1;
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end
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`RV32_INSTR_LH: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_read_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_HALF;
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mem_zero_extend_out = 0;
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rd_write_out = 1;
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end
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`RV32_INSTR_LW: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_read_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_WORD;
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rd_write_out = 1;
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end
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`RV32_INSTR_LBU: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_read_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_BYTE;
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mem_zero_extend_out = 1;
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rd_write_out = 1;
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end
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`RV32_INSTR_LHU: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_read_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_HALF;
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mem_zero_extend_out = 1;
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rd_write_out = 1;
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end
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`RV32_INSTR_SB: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_S;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_write_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_BYTE;
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end
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`RV32_INSTR_SH: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_S;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_write_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_HALF;
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end
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`RV32_INSTR_SW: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 1;
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imm_out = `RV32_IMM_S;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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mem_write_out = 1;
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mem_width_out = `RV32_MEM_WIDTH_WORD;
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end
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`RV32_INSTR_ADDI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLTI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_SLT;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLTIU: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_SLTU;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_XORI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_XOR;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_ORI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_OR;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_ANDI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_I;
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alu_op_out = `RV32_ALU_OP_AND;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLLI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_SHAMT;
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alu_op_out = `RV32_ALU_OP_SLL;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_SRLI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_SHAMT;
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alu_op_out = `RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_SRAI: begin
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valid_out = 1;
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rs1_read_out = 1;
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imm_out = `RV32_IMM_SHAMT;
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alu_op_out = `RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_IMM;
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rd_write_out = 1;
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end
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`RV32_INSTR_ADD: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 2;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 0;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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rd_write_out = 1;
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end
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`RV32_INSTR_SUB: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 2;
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alu_op_out = `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLL: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 2;
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alu_op_out = `RV32_ALU_OP_SLL;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLT: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 2;
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alu_op_out = `RV32_ALU_OP_SLT;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
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rd_write_out = 1;
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end
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`RV32_INSTR_SLTU: begin
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valid_out = 1;
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rs1_read_out = 1;
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rs2_read_out = 2;
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alu_op_out = `RV32_ALU_OP_SLTU;
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alu_sub_sra_out = 1;
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alu_src1_out = `RV32_ALU_SRC1_REG;
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alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_XOR: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
rs2_read_out = 2;
|
|
alu_op_out = `RV32_ALU_OP_XOR;
|
|
alu_src1_out = `RV32_ALU_SRC1_REG;
|
|
alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_SRL: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
rs2_read_out = 2;
|
|
alu_op_out = `RV32_ALU_OP_SRL_SRA;
|
|
alu_sub_sra_out = 0;
|
|
alu_src1_out = `RV32_ALU_SRC1_REG;
|
|
alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_SRA: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
rs2_read_out = 2;
|
|
alu_op_out = `RV32_ALU_OP_SRL_SRA;
|
|
alu_sub_sra_out = 1;
|
|
alu_src1_out = `RV32_ALU_SRC1_REG;
|
|
alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_OR: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
rs2_read_out = 2;
|
|
alu_op_out = `RV32_ALU_OP_OR;
|
|
alu_src1_out = `RV32_ALU_SRC1_REG;
|
|
alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_AND: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
rs2_read_out = 2;
|
|
alu_op_out = `RV32_ALU_OP_AND;
|
|
alu_src1_out = `RV32_ALU_SRC1_REG;
|
|
alu_src2_out = `RV32_ALU_SRC2_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_FENCE: begin
|
|
valid_out = 1;
|
|
end
|
|
`RV32_INSTR_FENCE_I: begin
|
|
valid_out = 1;
|
|
mem_fence_out = 1;
|
|
end
|
|
`RV32_INSTR_ECALL: begin
|
|
valid_out = 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_EBREAK: begin
|
|
valid_out = 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_MRET: begin
|
|
valid_out = 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_WFI: begin
|
|
valid_out = 1;
|
|
end
|
|
`RV32_INSTR_CSRRW: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
csr_read_out = |rd_in;
|
|
csr_write_out = 1;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RW;
|
|
csr_src_out = `RV32_CSR_SRC_REG;
|
|
rd_write_out = |rd_in;
|
|
end
|
|
`RV32_INSTR_CSRRS: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
csr_read_out = 1;
|
|
csr_write_out = |rs1_in;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RS;
|
|
csr_src_out = `RV32_CSR_SRC_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_CSRRC: begin
|
|
valid_out = 1;
|
|
rs1_read_out = 1;
|
|
csr_read_out = 1;
|
|
csr_write_out = |rs1_in;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RC;
|
|
csr_src_out = `RV32_CSR_SRC_REG;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_CSRRWI: begin
|
|
valid_out = 1;
|
|
imm_out = `RV32_IMM_ZIMM;
|
|
csr_read_out = |rd_in;
|
|
csr_write_out = 1;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RW;
|
|
csr_src_out = `RV32_CSR_SRC_IMM;
|
|
rd_write_out = |rd_in;
|
|
end
|
|
`RV32_INSTR_CSRRSI: begin
|
|
valid_out = 1;
|
|
imm_out = `RV32_IMM_ZIMM;
|
|
csr_read_out = 1;
|
|
csr_write_out = |rs1_in;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RS;
|
|
csr_src_out = `RV32_CSR_SRC_IMM;
|
|
rd_write_out = 1;
|
|
end
|
|
`RV32_INSTR_CSRRCI: begin
|
|
valid_out = 1;
|
|
imm_out = `RV32_IMM_ZIMM;
|
|
csr_read_out = 1;
|
|
csr_write_out = |rs1_in;
|
|
csr_write_op_out = `RV32_CSR_WRITE_OP_RC;
|
|
csr_src_out = `RV32_CSR_SRC_IMM;
|
|
rd_write_out = 1;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
`endif
|