118 lines
2.8 KiB
Systemverilog
118 lines
2.8 KiB
Systemverilog
`ifndef RV32_EXECUTE
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`define RV32_EXECUTE
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`include "rv32_alu.sv"
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`include "rv32_branch.sv"
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module rv32_execute (
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input clk,
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/* control in */
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input [4:0] rs1_in,
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input [4:0] rs2_in,
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input [3:0] alu_op_in,
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input alu_sub_sra_in,
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input alu_src1_in,
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input alu_src2_in,
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input mem_read_en_in,
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input mem_write_en_in,
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input [1:0] mem_width_in,
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input mem_zero_extend_in,
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input [1:0] branch_op_in,
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input branch_pc_src_in,
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input [4:0] rd_in,
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input rd_writeback_in,
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/* control in (from writeback) */
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input [4:0] writeback_rd_in,
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input writeback_rd_writeback_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] rs2_value_in,
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input [31:0] imm_in,
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/* data in (from writeback) */
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input [31:0] writeback_rd_value_in,
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/* control out */
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output mem_read_en_out,
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output mem_write_en_out,
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output [1:0] mem_width_out,
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output mem_zero_extend_out,
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output [1:0] branch_op_out,
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output [4:0] rd_out,
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output rd_writeback_out,
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/* data out */
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output [31:0] result_out,
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output [31:0] rs2_value_out,
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output [31:0] branch_pc_out
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);
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logic [31:0] rs1_value;
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logic [31:0] rs2_value;
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always_comb begin
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if (rd_writeback_out && rd_out == rs1_in && |rs1_in)
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rs1_value = result_out;
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else if (writeback_rd_writeback_in && writeback_rd_in == rs1_in && |rs1_in)
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rs1_value = writeback_rd_value_in;
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else
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rs1_value = rs1_value_in;
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if (rd_writeback_out && rd_out == rs2_in && |rs2_in)
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rs2_value = result_out;
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else if (writeback_rd_writeback_in && writeback_rd_in == rs2_in && |rs2_in)
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rs2_value = writeback_rd_value_in;
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else
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rs2_value = rs2_value_in;
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end
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rv32_alu alu (
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.clk(clk),
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/* control in */
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.op_in(alu_op_in),
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.sub_sra_in(alu_sub_sra_in),
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.src1_in(alu_src1_in),
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.src2_in(alu_src2_in),
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/* data in */
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.pc_in(pc_in),
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.rs1_value_in(rs1_value),
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.rs2_value_in(rs2_value),
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.imm_in(imm_in),
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/* data out */
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.result_out(result_out)
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);
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rv32_branch_pc_mux branch_pc_mux (
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.clk(clk),
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/* control in */
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.pc_src_in(branch_pc_src_in),
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/* data in */
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.pc_in(pc_in),
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.rs1_value_in(rs1_value_in),
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.imm_in(imm_in),
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/* data out */
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.pc_out(branch_pc_out)
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);
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always_ff @(posedge clk) begin
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mem_read_en_out <= mem_read_en_in;
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mem_write_en_out <= mem_write_en_in;
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mem_width_out <= mem_width_in;
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mem_zero_extend_out <= mem_zero_extend_in;
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branch_op_out <= branch_op_in;
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rd_out <= rd_in;
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rd_writeback_out <= rd_writeback_in;
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rs2_value_out <= rs2_value_in;
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end
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endmodule
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`endif
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