94 lines
2 KiB
Systemverilog
94 lines
2 KiB
Systemverilog
`include "clk_div.sv"
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`include "ram.sv"
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`include "rv32.sv"
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module top (
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input clk,
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/* serial flash */
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output flash_clk,
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output flash_csn,
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inout flash_io0,
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inout flash_io1,
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/* LEDs */
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output [7:0] leds,
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/* UART */
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input uart_rx,
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output uart_tx
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);
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logic flash_io0_en;
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logic flash_io0_in;
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logic flash_io0_out;
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logic flash_io1_en;
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logic flash_io1_in;
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logic flash_io1_out;
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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) flash_io [1:0] (
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.PACKAGE_PIN({flash_io1, flash_io0}),
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.OUTPUT_ENABLE({flash_io1_en, flash_io0_en}),
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.D_IN_0({flash_io1_in, flash_io0_in}),
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.D_OUT_0({flash_io1_out, flash_io0_out})
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);
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logic clk_slow;
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clk_div #(
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.LOG_DIVISOR(18)
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) clk_div (
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.clk_in(clk),
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.clk_out(clk_slow)
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);
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rv32 rv32 (
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.clk(clk_slow),
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/* control out */
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.write_mask_out(mem_write_mask),
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/* data in */
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.read_value_in(mem_read_value),
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/* data out */
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.address_out(mem_address),
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.write_value_out(mem_write_value)
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);
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/* memory bus control */
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logic [3:0] mem_write_mask;
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/* memory bus data */
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logic [31:0] mem_address;
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logic [31:0] mem_read_value = ram_read_value | leds_read_value;
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logic [31:0] mem_write_value;
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logic ram_sel = mem_address[31:0] == 32'b00000000_00000000_????????_????????;
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logic [31:0] ram_read_value;
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ram ram (
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.clk(clk_slow),
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/* control in */
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.sel_in(ram_sel),
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.write_mask_in(mem_write_mask),
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/* data in */
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.address_in(mem_address),
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.write_value_in(mem_write_value),
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/* data out */
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.read_value_out(ram_read_value)
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);
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logic leds_sel = mem_address[31:0] == 32'b00000000_00000001_00000000_000000??;
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logic [31:0] leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
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always_ff @(posedge clk_slow) begin
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if (leds_sel && mem_write_mask[0])
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leds <= mem_write_value[7:0];
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end
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endmodule
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