04dc25c5dc
I don't think the control/data in/out split makes as much sense - it's a convention much better suited to the pipeline stages.
38 lines
905 B
Systemverilog
38 lines
905 B
Systemverilog
`ifndef RAM
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`define RAM
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module ram (
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input clk,
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/* memory bus */
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input [31:0] address_in,
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input sel_in,
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output logic [31:0] read_value_out,
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input [3:0] write_mask_in,
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input [31:0] write_value_in
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);
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logic [31:0] mem [2047:0];
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logic [31:0] read_value;
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assign read_value_out = sel_in ? read_value : 0;
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always_ff @(negedge clk) begin
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read_value <= mem[address_in[31:2]];
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if (sel_in) begin
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if (write_mask_in[3])
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mem[address_in[31:2]][31:24] <= write_value_in[31:24];
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if (write_mask_in[2])
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mem[address_in[31:2]][23:16] <= write_value_in[23:16];
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if (write_mask_in[1])
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mem[address_in[31:2]][15:8] <= write_value_in[15:8];
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if (write_mask_in[0])
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mem[address_in[31:2]][7:0] <= write_value_in[7:0];
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end
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end
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endmodule
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`endif
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