54 lines
1.1 KiB
Systemverilog
54 lines
1.1 KiB
Systemverilog
`ifndef RV32_BRANCH
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`define RV32_BRANCH
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`define RV32_BRANCH_OP_NEVER 2'b00
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`define RV32_BRANCH_OP_ZERO 2'b01
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`define RV32_BRANCH_OP_NON_ZERO 2'b10
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`define RV32_BRANCH_OP_ALWAYS 2'b11
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`define RV32_BRANCH_PC_SRC_IMM 1'b0
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`define RV32_BRANCH_PC_SRC_REG 1'b1
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module rv32_branch_pc_mux (
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/* control in */
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input pc_src_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] imm_in,
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/* data out */
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output logic [31:0] pc_out
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);
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logic [31:0] pc;
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assign pc = (pc_src_in ? rs1_value_in : pc_in) + imm_in;
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assign pc_out = {pc[31:1], 1'b0};
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endmodule
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module rv32_branch_unit (
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/* control in */
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input [1:0] op_in,
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/* data in */
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input [31:0] result_in,
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/* control out */
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output logic taken_out
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);
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logic non_zero;
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assign non_zero = |result_in;
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always_comb begin
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case (op_in)
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`RV32_BRANCH_OP_NEVER: taken_out = 0;
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`RV32_BRANCH_OP_ZERO: taken_out = ~non_zero;
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`RV32_BRANCH_OP_NON_ZERO: taken_out = non_zero;
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`RV32_BRANCH_OP_ALWAYS: taken_out = 1;
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endcase
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end
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endmodule
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`endif
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