60 lines
1.2 KiB
Systemverilog
60 lines
1.2 KiB
Systemverilog
`ifndef RV32_MEM
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`define RV32_MEM
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`include "rv32_branch.sv"
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module rv32_mem (
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input clk,
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/* control in */
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input read_en_in,
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input write_en_in,
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input [1:0] branch_op_in,
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input [4:0] rd_in,
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input rd_writeback_in,
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/* data in */
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input [31:0] result_in,
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input [31:0] rs2_value_in,
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input [31:0] branch_pc_in,
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/* control out */
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output read_en_out,
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output branch_taken_out,
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output [4:0] rd_out,
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output rd_writeback_out,
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/* data out */
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output [31:0] result_out,
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output [31:0] read_value_out,
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output [31:0] branch_pc_out
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);
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logic [31:0] data_mem [255:0];
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rv32_branch branch (
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/* control in */
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.op_in(branch_op_in),
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/* data in */
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.result_in(result_in),
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/* control out */
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.taken_out(branch_taken_out)
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);
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assign branch_pc_out = branch_pc_in;
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always_ff @(posedge clk) begin
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read_en_out <= read_en_in;
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rd_out <= rd_in;
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rd_writeback_out <= rd_writeback_in;
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result_out <= result_in;
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read_value_out <= data_mem[result_in[31:2]];
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if (write_en_in)
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data_mem[result_in[31:2]] <= rs2_value_in;
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end
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endmodule
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`endif
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