Reset {rs1,rs2_out} when flushing the decode stage

This will prevent us needing to stall the pipeline for a load
instruction if the rs1/rs2 registers happened to match the rd register.

rv32_decode.sv

@@ -487,6 +487,8 @@ module rv32_decode (
             endcase
 
             if (flush) begin
+                rs1_out <= 0;
+                rs2_out <= 0;
                 mem_read_en_out <= 0;
                 mem_write_en_out <= 0;
                 branch_op_out <= RV32_BRANCH_OP_NEVER;