pingu_98/icicle
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Reset {rs1,rs2_out} when flushing the decode stage

Browse source 
This will prevent us needing to stall the pipeline for a load
instruction if the rs1/rs2 registers happened to match the rd register.
This commit is contained in:
Graham Edgecombe 2017-12-03 21:03:19 +00:00
parent eff39ad19b
commit 02f1d705b7
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
rv32_decode.sv
View file

@ -487,6 +487,8 @@ module rv32_decode (
endcase endcase
if (flush) begin if (flush) begin
rs1_out <= 0;
rs2_out <= 0;
mem_read_en_out <= 0; mem_read_en_out <= 0;
mem_write_en_out <= 0; mem_write_en_out <= 0;
branch_op_out <= RV32_BRANCH_OP_NEVER; branch_op_out <= RV32_BRANCH_OP_NEVER;