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Fix compatibility with iverilog

Browse source 
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
This commit is contained in:
Graham Edgecombe 2017-12-09 21:03:45 +00:00
parent de54271076
commit 22bce1bdeb
14 changed files with 231 additions and 182 deletions
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2
clk_div.sv
View file

@ -5,7 +5,7 @@ module clk_div #(
parameter LOG_DIVISOR = 1
) (
input clk_in,
output clk_out
output logic clk_out
);
logic [LOG_DIVISOR-1:0] q;

2
ram.sv
View file

@ -13,7 +13,7 @@ module ram (
input [31:0] write_value_in,
/* data out */
output [31:0] read_value_out
output logic [31:0] read_value_out
);
logic [31:0] mem [2047:0];
logic [31:0] read_value;

154
rv32.sv
View file

@ -11,16 +11,89 @@ module rv32 (
input clk,
/* control out (memory bus) */
output read_out,
output [3:0] write_mask_out,
output logic read_out,
output logic [3:0] write_mask_out,
/* data in (memory bus) */
input [31:0] read_value_in,
/* data out (memory bus) */
output [31:0] address_out,
output [31:0] write_value_out
output logic [31:0] address_out,
output logic [31:0] write_value_out
);
/* hazard -> fetch control */
logic fetch_stall;
logic fetch_flush;
/* hazard -> decode control */
logic decode_stall;
logic decode_flush;
/* hazard -> execute control */
logic execute_stall;
logic execute_flush;
/* hazard -> mem control */
logic mem_stall;
logic mem_flush;
/* fetch -> decode data */
logic [31:0] fetch_pc;
logic [31:0] fetch_instr;
/* decode -> hazard control */
logic [4:0] decode_rs1_unreg;
logic [4:0] decode_rs2_unreg;
/* decode -> execute control */
logic [4:0] decode_rs1;
logic [4:0] decode_rs2;
logic [3:0] decode_alu_op;
logic decode_alu_sub_sra;
logic decode_alu_src1;
logic decode_alu_src2;
logic decode_mem_read;
logic decode_mem_write;
logic [1:0] decode_mem_width;
logic decode_mem_zero_extend;
logic [1:0] decode_branch_op;
logic decode_branch_pc_src;
logic [4:0] decode_rd;
logic decode_rd_write;
/* decode -> execute data */
logic [31:0] decode_pc;
logic [31:0] decode_rs1_value;
logic [31:0] decode_rs2_value;
logic [31:0] decode_imm;
/* execute -> mem control */
logic execute_mem_read;
logic execute_mem_write;
logic [1:0] execute_mem_width;
logic execute_mem_zero_extend;
logic [1:0] execute_branch_op;
logic [4:0] execute_rd;
logic execute_rd_write;
/* execute -> mem data */
logic [31:0] execute_result;
logic [31:0] execute_rs2_value;
logic [31:0] execute_branch_pc;
/* mem -> writeback control */
logic [4:0] mem_rd;
logic mem_rd_write;
/* mem -> fetch control */
logic mem_branch_taken;
/* mem -> writeback data */
logic [31:0] mem_rd_value;
/* mem -> fetch data */
logic [31:0] mem_branch_pc;
rv32_hazard hazard (
/* control in */
.decode_rs1_in(decode_rs1_unreg),
@ -46,22 +119,6 @@ module rv32 (
.mem_flush_out(mem_flush)
);
/* hazard -> fetch control */
logic fetch_stall;
logic fetch_flush;
/* hazard -> decode control */
logic decode_stall;
logic decode_flush;
/* hazard -> execute control */
logic execute_stall;
logic execute_flush;
/* hazard -> mem control */
logic mem_stall;
logic mem_flush;
rv32_fetch fetch (
.clk(clk),
@ -80,10 +137,6 @@ module rv32 (
.instr_out(fetch_instr)
);
/* fetch -> decode data */
logic [31:0] fetch_pc;
logic [31:0] fetch_instr;
rv32_decode decode (
.clk(clk),
@ -129,32 +182,6 @@ module rv32 (
.imm_out(decode_imm)
);
/* decode -> hazard control */
logic [4:0] decode_rs1_unreg;
logic [4:0] decode_rs2_unreg;
/* decode -> execute control */
logic [4:0] decode_rs1;
logic [4:0] decode_rs2;
logic [3:0] decode_alu_op;
logic decode_alu_sub_sra;
logic decode_alu_src1;
logic decode_alu_src2;
logic decode_mem_read;
logic decode_mem_write;
logic [1:0] decode_mem_width;
logic decode_mem_zero_extend;
logic [1:0] decode_branch_op;
logic decode_branch_pc_src;
logic [4:0] decode_rd;
logic decode_rd_write;
/* decode -> execute data */
logic [31:0] decode_pc;
logic [31:0] decode_rs1_value;
logic [31:0] decode_rs2_value;
logic [31:0] decode_imm;
rv32_execute execute (
.clk(clk),
@ -206,20 +233,6 @@ module rv32 (
.branch_pc_out(execute_branch_pc)
);
/* execute -> mem control */
logic execute_mem_read;
logic execute_mem_write;
logic [1:0] execute_mem_width;
logic execute_mem_zero_extend;
logic [1:0] execute_branch_op;
logic [4:0] execute_rd;
logic execute_rd_write;
/* execute -> mem data */
logic [31:0] execute_result;
logic [31:0] execute_rs2_value;
logic [31:0] execute_branch_pc;
rv32_mem mem (
.clk(clk),
@ -261,19 +274,6 @@ module rv32 (
.address_out(address_out),
.write_value_out(write_value_out)
);
/* mem -> writeback control */
logic [4:0] mem_rd;
logic mem_rd_write;
/* mem -> fetch control */
logic mem_branch_taken;
/* mem -> writeback data */
logic [31:0] mem_rd_value;
/* mem -> fetch data */
logic [31:0] mem_branch_pc;
endmodule
`endif

44
rv32_alu.sv
View file

@ -32,25 +32,43 @@ module rv32_alu (
input [31:0] imm_in,
/* data out */
output [31:0] result_out
output logic [31:0] result_out
);
logic [31:0] src1 = src1_in ? pc_in : rs1_value_in;
logic [31:0] src2 = src2_in ? imm_in : rs2_value_in;
logic [31:0] src1;
logic [31:0] src2;
logic src1_sign = src1[31];
logic src2_sign = src2[31];
logic src1_sign;
logic src2_sign;
logic [4:0] shamt = src2[4:0];
logic [4:0] shamt;
logic [32:0] add_sub = sub_sra_in ? src1 - src2 : src1 + src2;
logic [31:0] srl_sra = $signed({sub_sra_in ? src1_sign : 1'b0, src1}) >>> shamt;
logic [32:0] add_sub;
logic [31:0] srl_sra;
logic carry = add_sub[32];
logic sign = add_sub[31];
logic ovf = (!src1_sign && src2_sign && sign) || (src1_sign && !src2_sign && !sign);
logic carry;
logic sign;
logic ovf;
logic lt = sign != ovf;
logic ltu = carry;
logic lt;
logic ltu;
assign src1 = src1_in ? pc_in : rs1_value_in;
assign src2 = src2_in ? imm_in : rs2_value_in;
assign src1_sign = src1[31];
assign src2_sign = src2[31];
assign shamt = src2[4:0];
assign add_sub = sub_sra_in ? src1 - src2 : src1 + src2;
assign srl_sra = $signed({sub_sra_in ? src1_sign : 1'b0, src1}) >>> shamt;
assign carry = add_sub[32];
assign sign = add_sub[31];
assign ovf = (!src1_sign && src2_sign && sign) || (src1_sign && !src2_sign && !sign);
assign lt = sign != ovf;
assign ltu = carry;
always_comb begin
case (op_in)

11
rv32_branch.sv
View file

@ -19,10 +19,11 @@ module rv32_branch_pc_mux (
input [31:0] imm_in,
/* data out */
output [31:0] pc_out
output logic [31:0] pc_out
);
logic [31:0] pc = (pc_src_in ? rs1_value_in : pc_in) + imm_in;
logic [31:0] pc;
assign pc = (pc_src_in ? rs1_value_in : pc_in) + imm_in;
assign pc_out = {pc[31:1], 1'b0};
endmodule
@ -34,9 +35,11 @@ module rv32_branch (
input [31:0] result_in,
/* control out */
output taken_out
output logic taken_out
);
logic non_zero = |result_in;
logic non_zero;
assign non_zero = |result_in;
always_comb begin
case (op_in)

85
rv32_decode.sv
View file

@ -26,48 +26,65 @@ module rv32_decode (
input [31:0] rd_value_in,
/* control out (to hazard) */
output [4:0] rs1_unreg_out,
output [4:0] rs2_unreg_out,
output logic [4:0] rs1_unreg_out,
output logic [4:0] rs2_unreg_out,
/* control out */
output valid_out,
output [4:0] rs1_out,
output [4:0] rs2_out,
output [3:0] alu_op_out,
output alu_sub_sra_out,
output alu_src1_out,
output alu_src2_out,
output mem_read_out,
output mem_write_out,
output [1:0] mem_width_out,
output mem_zero_extend_out,
output [1:0] branch_op_out,
output branch_pc_src_out,
output [4:0] rd_out,
output rd_write_out,
output logic valid_out,
output logic [4:0] rs1_out,
output logic [4:0] rs2_out,
output logic [3:0] alu_op_out,
output logic alu_sub_sra_out,
output logic alu_src1_out,
output logic alu_src2_out,
output logic mem_read_out,
output logic mem_write_out,
output logic [1:0] mem_width_out,
output logic mem_zero_extend_out,
output logic [1:0] branch_op_out,
output logic branch_pc_src_out,
output logic [4:0] rd_out,
output logic rd_write_out,
/* data out */
output [31:0] pc_out,
output [31:0] rs1_value_out,
output [31:0] rs2_value_out,
output [31:0] imm_out
output logic [31:0] pc_out,
output logic [31:0] rs1_value_out,
output logic [31:0] rs2_value_out,
output logic [31:0] imm_out
);
logic [6:0] funct7 = instr_in[31:25];
logic [4:0] rs2 = instr_in[24:20];
logic [4:0] rs1 = instr_in[19:15];
logic [2:0] funct3 = instr_in[14:12];
logic [4:0] rd = instr_in[11:7];
logic [6:0] opcode = instr_in[6:0];
logic [6:0] funct7;
logic [4:0] rs2;
logic [4:0] rs1;
logic [2:0] funct3;
logic [4:0] rd;
logic [6:0] opcode;
logic sign = instr_in[31];
logic sign;
logic [31:0] imm_i = {{21{sign}}, instr_in[30:25], instr_in[24:21], instr_in[20]};
logic [31:0] imm_s = {{21{sign}}, instr_in[30:25], instr_in[11:8], instr_in[7]};
logic [31:0] imm_b = {{20{sign}}, instr_in[7], instr_in[30:25], instr_in[11:8], 1'b0};
logic [31:0] imm_u = {sign, instr_in[30:20], instr_in[19:12], 12'b0};
logic [31:0] imm_j = {{12{sign}}, instr_in[19:12], instr_in[20], instr_in[30:25], instr_in[24:21], 1'b0};
logic [31:0] imm_i;
logic [31:0] imm_s;
logic [31:0] imm_b;
logic [31:0] imm_u;
logic [31:0] imm_j;
logic [31:0] shamt = {27'bx, rs2};
logic [31:0] shamt;
assign funct7 = instr_in[31:25];
assign rs2 = instr_in[24:20];
assign rs1 = instr_in[19:15];
assign funct3 = instr_in[14:12];
assign rd = instr_in[11:7];
assign opcode = instr_in[6:0];
assign sign = instr_in[31];
assign imm_i = {{21{sign}}, instr_in[30:25], instr_in[24:21], instr_in[20]};
assign imm_s = {{21{sign}}, instr_in[30:25], instr_in[11:8], instr_in[7]};
assign imm_b = {{20{sign}}, instr_in[7], instr_in[30:25], instr_in[11:8], 1'b0};
assign imm_u = {sign, instr_in[30:20], instr_in[19:12], 12'b0};
assign imm_j = {{12{sign}}, instr_in[19:12], instr_in[20], instr_in[30:25], instr_in[24:21], 1'b0};
assign shamt = {27'bx, rs2};
assign rs1_unreg_out = rs1;
assign rs2_unreg_out = rs2;

20
rv32_execute.sv
View file

@ -41,18 +41,18 @@ module rv32_execute (
input [31:0] writeback_rd_value_in,
/* control out */
output mem_read_out,
output mem_write_out,
output [1:0] mem_width_out,
output mem_zero_extend_out,
output [1:0] branch_op_out,
output [4:0] rd_out,
output rd_write_out,
output logic mem_read_out,
output logic mem_write_out,
output logic [1:0] mem_width_out,
output logic mem_zero_extend_out,
output logic [1:0] branch_op_out,
output logic [4:0] rd_out,
output logic rd_write_out,
/* data out */
output [31:0] result_out,
output [31:0] rs2_value_out,
output [31:0] branch_pc_out
output logic [31:0] result_out,
output logic [31:0] rs2_value_out,
output logic [31:0] branch_pc_out
);
logic [31:0] rs1_value;
logic [31:0] rs2_value;

8
rv32_fetch.sv
View file

@ -17,17 +17,19 @@ module rv32_fetch (
input [31:0] branch_pc_in,
/* data out */
output [31:0] pc_out,
output [31:0] instr_out
output logic [31:0] pc_out,
output logic [31:0] instr_out
);
logic [31:0] instr_mem [255:0];
logic [31:0] next_pc;
logic [31:0] pc = branch_taken_in ? branch_pc_in : next_pc;
logic [31:0] pc;
initial
$readmemh("progmem_syn.hex", instr_mem);
assign pc = branch_taken_in ? branch_pc_in : next_pc;
always_ff @(posedge clk) begin
if (!stall_in) begin
instr_out <= instr_mem[pc[31:2]];

20
rv32_hazard.sv
View file

@ -13,19 +13,21 @@ module rv32_hazard (
input mem_branch_taken_in,
/* control out */
output fetch_stall_out,
output fetch_flush_out,
output logic fetch_stall_out,
output logic fetch_flush_out,
output decode_stall_out,
output decode_flush_out,
output logic decode_stall_out,
output logic decode_flush_out,
output execute_stall_out,
output execute_flush_out,
output logic execute_stall_out,
output logic execute_flush_out,
output mem_stall_out,
output mem_flush_out
output logic mem_stall_out,
output logic mem_flush_out
);
logic fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
logic fetch_wait_for_mem_read;
assign fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read;
assign fetch_flush_out = 0;

18
rv32_mem.sv
View file

@ -32,21 +32,21 @@ module rv32_mem (
input [31:0] read_value_in,
/* control out */
output branch_taken_out,
output [4:0] rd_out,
output rd_write_out,
output logic branch_taken_out,
output logic [4:0] rd_out,
output logic rd_write_out,
/* control out (to memory bus) */
output read_out,
output [3:0] write_mask_out,
output logic read_out,
output logic [3:0] write_mask_out,
/* data out */
output [31:0] rd_value_out,
output [31:0] branch_pc_out,
output logic [31:0] rd_value_out,
output logic [31:0] branch_pc_out,
/* data out (to memory bus) */
output [31:0] address_out,
output [31:0] write_value_out
output logic [31:0] address_out,
output logic [31:0] write_value_out
);
rv32_branch branch (
/* control in */

4
rv32_regs.sv
View file

@ -15,8 +15,8 @@ module rv32_regs (
input [31:0] rd_value_in,
/* data out */
output [31:0] rs1_value_out,
output [31:0] rs2_value_out
output logic [31:0] rs1_value_out,
output logic [31:0] rs2_value_out
);
logic [31:0] regs [31:0];

2
sync.sv
View file

@ -6,7 +6,7 @@ module sync #(
) (
input clk,
input [BITS-1:0] in,
output [BITS-1:0] out
output logic [BITS-1:0] out
);
logic [BITS-1:0] metastable;

36
top.sv
View file

@ -9,17 +9,17 @@ module top (
input clk,
/* serial flash */
output flash_clk,
output flash_csn,
output logic flash_clk,
output logic flash_csn,
inout flash_io0,
inout flash_io1,
/* LEDs */
output [7:0] leds,
output logic [7:0] leds,
/* UART */
input uart_rx,
output uart_tx
output logic uart_tx
);
logic flash_io0_en;
logic flash_io0_in;
@ -48,7 +48,9 @@ module top (
);
logic pll_locked;
logic reset = ~pll_locked;
logic reset;
assign reset = ~pll_locked;
sync sync (
.clk(pll_clk),
@ -56,6 +58,17 @@ module top (
.out(pll_locked)
);
/* memory bus control */
logic mem_read;
logic [3:0] mem_write_mask;
/* memory bus data */
logic [31:0] mem_address;
logic [31:0] mem_read_value;
logic [31:0] mem_write_value;
assign mem_read_value = ram_read_value | leds_read_value | uart_read_value;
rv32 rv32 (
.clk(pll_clk),
@ -71,15 +84,6 @@ module top (
.write_value_out(mem_write_value)
);
/* memory bus control */
logic mem_read;
logic [3:0] mem_write_mask;
/* memory bus data */
logic [31:0] mem_address;
logic [31:0] mem_read_value = ram_read_value | leds_read_value | uart_read_value;
logic [31:0] mem_write_value;
always_comb begin
ram_sel = 0;
leds_sel = 0;
@ -111,7 +115,9 @@ module top (
);
logic leds_sel;
logic [31:0] leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
logic [31:0] leds_read_value;
assign leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
always_ff @(posedge pll_clk) begin
if (leds_sel && mem_write_mask[0])

7
uart.sv
View file

@ -11,7 +11,7 @@ module uart (
/* serial port */
input rx_in,
output tx_out,
output logic tx_out,
/* control in */
input sel_in,
@ -23,7 +23,7 @@ module uart (
input [31:0] write_value_in,
/* data out */
output [31:0] read_value_out
output logic [31:0] read_value_out
);
logic [15:0] clk_div;
@ -38,12 +38,13 @@ module uart (
logic [3:0] tx_bits;
logic [9:0] tx_buf;
logic tx_write_ready = ~|tx_bits;
logic tx_write_ready;
initial
tx_buf[0] = 1;
assign tx_out = tx_buf[0];
assign tx_write_ready = ~|tx_bits;
always_comb begin
if (sel_in) begin