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32-bit RISC-V system on chip for iCE40 FPGAs
84 commits 1 branch 0 tags 149 KiB
SystemVerilog 96.1%
Makefile 2.3%
C 0.9%
Assembly 0.4%
Tcl 0.3%
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Graham Edgecombe 22bce1bdeb Fix compatibility with iverilog 
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
.gitignore Store icebox_stat output in top.stat 2017-12-07 22:37:58 +00:00
clk_div.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf Add serial flash, LED and UART pins 2017-12-01 23:25:06 +00:00
Makefile Move timing closure requirement to the flash target 2017-12-07 22:37:58 +00:00
progmem.s Add UART demo program 2017-12-07 22:37:59 +00:00
ram.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_alu.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_branch.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_decode.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_execute.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_fetch.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_hazard.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_mem.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_opcodes.sv Replace localparams at the root level with defines 2017-12-09 10:44:39 +00:00
rv32_regs.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
sync.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
top.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
top.ys Pass -full to opt 2017-12-08 22:29:22 +00:00
uart.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00