pingu_98/icicle
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Memory map the LEDs

Browse source
This commit is contained in:
Graham Edgecombe 2017-12-06 08:14:42 +00:00
parent 0be0da3917
commit 365d3e37c6
3 changed files with 12 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
progmem.s
View file

@ -15,5 +15,6 @@ mul_even:
# display results on the LEDs # display results on the LEDs
mul_done: mul_done:
mv t6, t3 li t1, 0x00010000
sw t3, 0(t1)
j . j .

6
rv32.sv
View file

@ -9,7 +9,6 @@
module rv32 ( module rv32 (
input clk, input clk,
output [7:0] leds,
/* control out (memory bus) */ /* control out (memory bus) */
output [3:0] write_mask_out, output [3:0] write_mask_out,
@ -21,11 +20,6 @@ module rv32 (
output [31:0] address_out, output [31:0] address_out,
output [31:0] write_value_out output [31:0] write_value_out
); );
always_ff @(posedge clk) begin
if (mem_rd_writeback && mem_rd == 31)
leds <= mem_rd_value[7:0];
end
rv32_hazard hazard ( rv32_hazard hazard (
/* control in */ /* control in */
.decode_rs1_in(decode_rs1_unreg), .decode_rs1_in(decode_rs1_unreg),

13
top.sv
View file

@ -46,7 +46,6 @@ module top (
rv32 rv32 ( rv32 rv32 (
.clk(clk_slow), .clk(clk_slow),
.leds(leds),
/* control out */ /* control out */
.write_mask_out(mem_write_mask), .write_mask_out(mem_write_mask),
@ -64,10 +63,10 @@ module top (
/* memory bus data */ /* memory bus data */
logic [31:0] mem_address; logic [31:0] mem_address;
logic [31:0] mem_read_value = ram_read_value; logic [31:0] mem_read_value = ram_read_value | leds_read_value;
logic [31:0] mem_write_value; logic [31:0] mem_write_value;
logic ram_sel = mem_address[31:16] == 0; logic ram_sel = mem_address[31:0] == 32'b00000000_00000000_????????_????????;
logic [31:0] ram_read_value; logic [31:0] ram_read_value;
ram ram ( ram ram (
@ -84,4 +83,12 @@ module top (
/* data out */ /* data out */
.read_value_out(ram_read_value) .read_value_out(ram_read_value)
); );
logic leds_sel = mem_address[31:0] == 32'b00000000_00000001_00000000_000000??;
logic [31:0] leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
always_ff @(posedge clk) begin
if (leds_sel && mem_write_mask[0])
leds <= mem_write_value[7:0];
end
endmodule endmodule