Remove redundant logic keyword from the top module

2017-12-01 22:59:43 +00:00 · 2017-12-01 22:59:43 +00:00 · 9ca70b76a6
commit 9ca70b76a6
parent 5884a437b8
1 changed files with 1 additions and 1 deletions
--- a/top.sv
+++ b/top.sv
@ -1,7 +1,7 @@
 `include "rv32.sv"

 module top (
-    input logic clk
+    input clk
 );
    rv32 rv32 (
        .clk(clk)