9 lines
101 B
Systemverilog
9 lines
101 B
Systemverilog
`include "rv32.sv"
|
|
|
|
module top (
|
|
input clk
|
|
);
|
|
rv32 rv32 (
|
|
.clk(clk)
|
|
);
|
|
endmodule
|