icicle/top.sv

`include "rv32.sv"

module top (
    input clk
);
    rv32 rv32 (
        .clk(clk)
    );
endmodule
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`include "rv32.sv"

			`module top (`
Remove redundant logic keyword from the top module 2017-12-01 22:59:43 +00:00			`input clk`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`);`
			`rv32 rv32 (`
			`.clk(clk)`
			`);`
			`endmodule`