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support up5k FPGA with internal OSC

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This commit is contained in:
Andrea Venturi 2018-01-23 18:17:44 +01:00
parent f5a046f678
commit a9c0d91341
3 changed files with 23 additions and 9 deletions
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15
Makefile
View file

@ -3,7 +3,7 @@ PLL = pll.sv
SRC = $(sort $(wildcard *.sv) $(PLL)) SRC = $(sort $(wildcard *.sv) $(PLL))
TOP = top TOP = top
SV = $(TOP).sv SV = $(TOP).sv
YS = $(TOP).ys TCL := $(TOP).tcl
YS_ICE40 = `yosys-config --datdir/ice40/cells_sim.v` YS_ICE40 = `yosys-config --datdir/ice40/cells_sim.v`
BLIF = $(TOP).blif BLIF = $(TOP).blif
ASC_SYN = $(TOP)_syn.asc ASC_SYN = $(TOP)_syn.asc
@ -30,6 +30,14 @@ OBJCOPY = $(TARGET)-objcopy
all: $(BIN) all: $(BIN)
upduino: SPEED=up
upduino: DEVICE=5k
upduino: PACKAGE=sg48
upduino: PCF=ice40up5k-upduino.pcf
upduino: FREQ_OSC=48
upduino: clean all
@echo "executing yosys script $(YS)"
clean: clean:
$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) $(TIME_RPT) $(STAT) progmem_syn.hex progmem.hex progmem.o start.o progmem $(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) $(TIME_RPT) $(STAT) progmem_syn.hex progmem.hex progmem.o start.o progmem
@ -46,8 +54,9 @@ progmem_syn.hex:
$(PLL): $(PLL):
icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@ icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
$(BLIF): $(YS) $(SRC) progmem_syn.hex $(BLIF): $(TCL) $(SRC) progmem_syn.hex
yosys $(QUIET) -s $< @echo "device is $(DEVICE)"
IC=$(SPEED)$(DEVICE) yosys $(QUIET) $<
syntax: $(SRC) progmem_syn.hex syntax: $(SRC) progmem_syn.hex
iverilog -Wall -t null -g2012 $(YS_ICE40) $(SV) iverilog -Wall -t null -g2012 $(YS_ICE40) $(SV)

11
top.sv
View file

@ -6,7 +6,9 @@
`include "uart.sv" `include "uart.sv"
module top ( module top (
`ifndef up5k
input clk, input clk,
`endif
/* serial flash */ /* serial flash */
output logic flash_clk, output logic flash_clk,
@ -29,6 +31,15 @@ module top (
logic flash_io1_in; logic flash_io1_in;
logic flash_io1_out; logic flash_io1_out;
`ifdef up5k
wire clk;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(clk)
);
`endif
SB_IO #( SB_IO #(
.PIN_TYPE(6'b1010_01) .PIN_TYPE(6'b1010_01)
) flash_io [1:0] ( ) flash_io [1:0] (

6
top.ys
View file

@ -1,6 +0,0 @@
read_verilog -noautowire -sv top.sv
proc
opt -full
alumacc
share -aggressive
synth_ice40 -abc2 -top top -blif top.blif