4 commits

Author	SHA1	Message	Date
Graham Edgecombe	276688f9ef	Move CSR access to the execute stage ... This reduces the amount of logic slightly, and also removes the one cycle delay between a CSR read and a subsequent instruction reading from the destination register.	2017-12-30 11:34:14 +00:00
Graham Edgecombe	eac6a20040	Only stall the pipeline if rs1/rs2 are read	2017-12-29 20:37:02 +00:00
Graham Edgecombe	4b6218c2a8	Add initial CSR support	2017-12-29 15:29:15 +00:00
Graham Edgecombe	0013935bb0	Split decode stage into smaller modules ... This increases the number of LUTs slightly (by ~20), as the immediate mux is now separate to the main control unit, but I think it's worth the cost. The imm output is also renamed to imm_value. This is consistent with rs1_value and rs2_value, and avoids a collision with the new imm output, which represents the type of immediate.	2017-12-27 14:05:09 +00:00