Commit graph

5 commits

Author SHA1 Message Date
Graham Edgecombe
276688f9ef Move CSR access to the execute stage
This reduces the amount of logic slightly, and also removes the one
cycle delay between a CSR read and a subsequent instruction reading from
the destination register.
2017-12-30 11:34:14 +00:00
Graham Edgecombe
3f19fc4226 Replace parallel 32-bit adders with a single 64-bit adder 2017-12-29 17:24:04 +00:00
Graham Edgecombe
21e7ee2b8c Remove unused stall_in input from rv32_csrs 2017-12-29 16:26:11 +00:00
Graham Edgecombe
63cd024d5c Fix instret rollover 2017-12-29 16:23:33 +00:00
Graham Edgecombe
4b6218c2a8 Add initial CSR support 2017-12-29 15:29:15 +00:00