26 lines
533 B
Systemverilog
26 lines
533 B
Systemverilog
module rv32_regs (
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input clk,
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/* control in */
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input [4:0] rs1_in,
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input [4:0] rs2_in,
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input [4:0] rd_in,
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input rd_writeback_in,
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/* data in */
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input [31:0] rd_value_in,
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/* data out */
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output [31:0] rs1_value_out,
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output [31:0] rs2_value_out
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);
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logic [31:0] regs [31:0];
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always_ff @(posedge clk) begin
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rs1_value_out <= regs[rs1_in];
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rs2_value_out <= regs[rs2_in];
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if (rd_writeback_in && |rd_in)
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regs[rd_in] <= rd_value_in;
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end
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endmodule
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