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32-bit RISC-V system on chip for iCE40 FPGAs
1 commit 1 branch 0 tags 149 KiB
SystemVerilog 96.1%
Makefile 2.3%
C 0.9%
Assembly 0.4%
Tcl 0.3%
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Graham Edgecombe 4a4dee334d Add initial fetch/decode stages
2017-12-01 08:46:43 +00:00
.gitignore Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
ice40hx8k-b-evn.pcf Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
Makefile Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
rv32.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
rv32_decode.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
rv32_fetch.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
rv32_opcodes.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
rv32_regs.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
top.sv Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00
top.ys Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00