276688f9ef
This reduces the amount of logic slightly, and also removes the one cycle delay between a CSR read and a subsequent instruction reading from the destination register.
72 lines
2 KiB
Systemverilog
72 lines
2 KiB
Systemverilog
`ifndef RV32_CSRS
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`define RV32_CSRS
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/* |rw|pl| id | */
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`define RV32_CSR_CYCLE 12'b11_00_00000000
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`define RV32_CSR_TIME 12'b11_00_00000001
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`define RV32_CSR_INSTRET 12'b11_00_00000010
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`define RV32_CSR_CYCLEH 12'b11_00_10000000
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`define RV32_CSR_TIMEH 12'b11_00_10000001
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`define RV32_CSR_INSTRETH 12'b11_00_10000010
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`define RV32_CSR_WRITE_OP_RW 2'b00
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`define RV32_CSR_WRITE_OP_RS 2'b01
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`define RV32_CSR_WRITE_OP_RC 2'b10
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`define RV32_CSR_SRC_IMM 1'b0
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`define RV32_CSR_SRC_REG 1'b1
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module rv32_csrs (
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input clk,
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/* control in */
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input read_in,
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input write_in,
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input [1:0] write_op_in,
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input src_in,
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/* control in (from writeback) */
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input instr_retired_in,
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/* data in */
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input [11:0] csr_in,
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input [31:0] rs1_value_in,
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input [31:0] imm_value_in,
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/* data out */
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output logic [31:0] read_value_out
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);
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logic [31:0] write_value;
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logic [31:0] new_value;
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logic [63:0] cycle;
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logic [63:0] instret;
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assign write_value = src_in ? imm_value_in : rs1_value_in;
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always_comb begin
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case (csr_in)
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`RV32_CSR_CYCLE: read_value_out = cycle[31:0];
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`RV32_CSR_TIME: read_value_out = cycle[31:0];
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`RV32_CSR_INSTRET: read_value_out = instret[31:0];
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`RV32_CSR_CYCLEH: read_value_out = cycle[63:32];
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`RV32_CSR_TIMEH: read_value_out = cycle[63:32];
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`RV32_CSR_INSTRETH: read_value_out = instret[63:32];
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default: read_value_out = 32'bx;
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endcase
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case (write_op_in)
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`RV32_CSR_WRITE_OP_RW: new_value = write_value;
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`RV32_CSR_WRITE_OP_RS: new_value = read_value_out | write_value;
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`RV32_CSR_WRITE_OP_RC: new_value = read_value_out & ~write_value;
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default: new_value = 32'bx;
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endcase
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end
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always_ff @(posedge clk) begin
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cycle <= cycle + 1;
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instret <= instret + instr_retired_in;
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end
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endmodule
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`endif
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