59 lines
1.7 KiB
Systemverilog
59 lines
1.7 KiB
Systemverilog
`ifndef RV32_ALU
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`define RV32_ALU
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`include "rv32_alu_ops.sv"
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module rv32_alu (
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input clk,
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/* control in */
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input [3:0] op_in,
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input sub_sra_in,
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input src1_in,
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input src2_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] rs2_value_in,
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input [31:0] imm_in,
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/* data out */
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output [31:0] result_out
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);
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logic [31:0] src1 = src1_in ? pc_in : rs1_value_in;
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logic [31:0] src2 = src2_in ? imm_in : rs2_value_in;
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logic src1_sign = src1[31];
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logic src2_sign = src2[31];
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logic [4:0] shamt = src2[4:0];
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logic [32:0] add_sub = sub_sra_in ? src1 - src2 : src1 + src2;
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logic [31:0] srl_sra = $signed({sub_sra_in ? src1_sign : 1'b0, src1}) >>> shamt;
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logic carry = add_sub[32];
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logic sign = add_sub[31];
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logic ovf = (!src1_sign && src2_sign && sign) || (src1_sign && !src2_sign && !sign);
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logic lt = sign != ovf;
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logic ltu = carry;
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always_ff @(posedge clk) begin
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case (op_in)
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RV32_ALU_OP_ADD_SUB: result_out <= add_sub[31:0];
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RV32_ALU_OP_XOR: result_out <= src1 ^ src2;
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RV32_ALU_OP_OR: result_out <= src1 | src2;
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RV32_ALU_OP_AND: result_out <= src1 & src2;
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RV32_ALU_OP_SLL: result_out <= src1 << shamt;
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RV32_ALU_OP_SRL_SRA: result_out <= srl_sra;
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RV32_ALU_OP_SLT: result_out <= {31'b0, lt};
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RV32_ALU_OP_SLTU: result_out <= {31'b0, ltu};
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RV32_ALU_OP_SRC1P4: result_out <= src1 + 4;
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RV32_ALU_OP_SRC2: result_out <= src2;
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default: result_out <= 32'bx;
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endcase
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end
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endmodule
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`endif
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