32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 965311c1e5 Add mem_ prefix to the hazard unit's branch_taken input		2017-12-07 22:37:58 +00:00
.gitignore	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
clk_div.sv	Replace wire with logic	2017-12-07 22:37:58 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
progmem.s	Use 4 space indentation in the assembly file for consistency	2017-12-07 22:37:58 +00:00
rv32.sv	Add mem_ prefix to the hazard unit's branch_taken input	2017-12-07 22:37:58 +00:00
rv32_alu.sv	Remove clock input from ALU and branch PC mux	2017-12-07 22:37:58 +00:00
rv32_alu_ops.sv	Add include guards	2017-12-01 23:30:33 +00:00
rv32_branch.sv	Remove clock input from ALU and branch PC mux	2017-12-07 22:37:58 +00:00
rv32_branch_ops.sv	Add branching support	2017-12-02 15:23:12 +00:00
rv32_decode.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_execute.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_fetch.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_hazard.sv	Add mem_ prefix to the hazard unit's branch_taken input	2017-12-07 22:37:58 +00:00
rv32_mem.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_mem_ops.sv	Add LB, LBU, LH, LHU, SB and SH instructions	2017-12-07 22:37:58 +00:00
rv32_opcodes.sv	Add flush and stall inputs to every stage	2017-12-07 22:37:58 +00:00
rv32_regs.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
top.sv	Add clock divider	2017-12-07 22:37:58 +00:00
top.ys	Run abc twice to improve logic density	2017-12-07 22:37:58 +00:00