527 lines
19 KiB
Systemverilog
527 lines
19 KiB
Systemverilog
`ifndef RV32_DECODE
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`define RV32_DECODE
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`include "rv32_alu.sv"
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`include "rv32_branch.sv"
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`include "rv32_mem.sv"
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`include "rv32_opcodes.sv"
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`include "rv32_regs.sv"
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module rv32_decode (
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input clk,
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/* control in (from hazard) */
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input stall_in,
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input flush_in,
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/* control in (from writeback) */
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input [4:0] rd_in,
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input rd_write_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] instr_in,
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/* data in (from writeback) */
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input [31:0] rd_value_in,
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/* control out (to hazard) */
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output logic [4:0] rs1_unreg_out,
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output logic [4:0] rs2_unreg_out,
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/* control out */
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output logic valid_out,
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output logic [4:0] rs1_out,
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output logic [4:0] rs2_out,
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output logic [3:0] alu_op_out,
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output logic alu_sub_sra_out,
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output logic alu_src1_out,
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output logic alu_src2_out,
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output logic mem_read_out,
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output logic mem_write_out,
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output logic [1:0] mem_width_out,
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output logic mem_zero_extend_out,
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output logic [1:0] branch_op_out,
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output logic branch_pc_src_out,
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output logic [4:0] rd_out,
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output logic rd_write_out,
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/* data out */
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output logic [31:0] pc_out,
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output logic [31:0] rs1_value_out,
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output logic [31:0] rs2_value_out,
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output logic [31:0] imm_out
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);
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logic [6:0] funct7;
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logic [4:0] rs2;
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logic [4:0] rs1;
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logic [2:0] funct3;
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logic [4:0] rd;
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logic [6:0] opcode;
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logic sign;
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logic [31:0] imm_i;
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logic [31:0] imm_s;
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logic [31:0] imm_b;
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logic [31:0] imm_u;
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logic [31:0] imm_j;
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logic [31:0] shamt;
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logic [31:0] zimm;
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assign funct7 = instr_in[31:25];
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assign rs2 = instr_in[24:20];
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assign rs1 = instr_in[19:15];
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assign funct3 = instr_in[14:12];
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assign rd = instr_in[11:7];
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assign opcode = instr_in[6:0];
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assign sign = instr_in[31];
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assign imm_i = {{21{sign}}, instr_in[30:25], instr_in[24:21], instr_in[20]};
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assign imm_s = {{21{sign}}, instr_in[30:25], instr_in[11:8], instr_in[7]};
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assign imm_b = {{20{sign}}, instr_in[7], instr_in[30:25], instr_in[11:8], 1'b0};
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assign imm_u = {sign, instr_in[30:20], instr_in[19:12], 12'b0};
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assign imm_j = {{12{sign}}, instr_in[19:12], instr_in[20], instr_in[30:25], instr_in[24:21], 1'b0};
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assign shamt = {27'bx, rs2};
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assign zimm = {27'b0, rs1};
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assign rs1_unreg_out = rs1;
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assign rs2_unreg_out = rs2;
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rv32_regs regs (
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.clk(clk),
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.stall_in(stall_in),
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/* control in */
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.rs1_in(rs1),
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.rs2_in(rs2),
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.rd_in(rd_in),
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.rd_write_in(rd_write_in),
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/* data in */
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.rd_value_in(rd_value_in),
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/* data out */
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.rs1_value_out(rs1_value_out),
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.rs2_value_out(rs2_value_out)
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);
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always_ff @(posedge clk) begin
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if (!stall_in) begin
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valid_out <= 0;
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rs1_out <= rs1;
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rs2_out <= rs2;
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alu_op_out <= 4'bx;
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alu_sub_sra_out <= 1'bx;
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alu_src1_out <= 1'bx;
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alu_src2_out <= 1'bx;
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mem_read_out <= 0;
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mem_write_out <= 0;
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mem_width_out <= 2'bx;
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mem_zero_extend_out <= 1'bx;
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branch_op_out <= `RV32_BRANCH_OP_NEVER;
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branch_pc_src_out <= 1'bx;
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rd_out <= rd;
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rd_write_out <= 0;
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pc_out <= pc_in;
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imm_out <= 32'bx;
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casez (instr_in)
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`RV32_INSTR_LUI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SRC2;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_u;
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end
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`RV32_INSTR_AUIPC: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_PC;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_u;
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end
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`RV32_INSTR_JAL: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SRC1P4;
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alu_src1_out <= `RV32_ALU_SRC1_PC;
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branch_op_out <= `RV32_BRANCH_OP_ALWAYS;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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rd_write_out <= 1;
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imm_out <= imm_j;
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end
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`RV32_INSTR_JALR: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SRC1P4;
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alu_src1_out <= `RV32_ALU_SRC1_PC;
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branch_op_out <= `RV32_BRANCH_OP_ALWAYS;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_REG;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_BEQ: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_BNE: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_BLT: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_BGE: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_BLTU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_BGEU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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branch_op_out <= `RV32_BRANCH_OP_ZERO;
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branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
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imm_out <= imm_b;
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end
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`RV32_INSTR_LB: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_read_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_BYTE;
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mem_zero_extend_out <= 0;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_LH: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_read_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_HALF;
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mem_zero_extend_out <= 0;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_LW: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_read_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_WORD;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_LBU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_read_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_BYTE;
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mem_zero_extend_out <= 1;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_LHU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_read_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_HALF;
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mem_zero_extend_out <= 1;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_SB: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_write_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_BYTE;
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imm_out <= imm_s;
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end
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`RV32_INSTR_SH: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_write_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_HALF;
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imm_out <= imm_s;
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end
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`RV32_INSTR_SW: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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mem_write_out <= 1;
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mem_width_out <= `RV32_MEM_WIDTH_WORD;
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imm_out <= imm_s;
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end
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`RV32_INSTR_ADDI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_SLTI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_SLTIU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_XORI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_XOR;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_ORI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_OR;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_ANDI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_AND;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= imm_i;
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end
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`RV32_INSTR_SLLI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLL;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= shamt;
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end
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`RV32_INSTR_SRLI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= shamt;
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end
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`RV32_INSTR_SRAI: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_IMM;
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rd_write_out <= 1;
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imm_out <= shamt;
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end
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`RV32_INSTR_ADD: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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rd_write_out <= 1;
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end
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`RV32_INSTR_SUB: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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rd_write_out <= 1;
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end
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`RV32_INSTR_SLL: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLL;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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rd_write_out <= 1;
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end
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`RV32_INSTR_SLT: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= `RV32_ALU_SRC1_REG;
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alu_src2_out <= `RV32_ALU_SRC2_REG;
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rd_write_out <= 1;
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end
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`RV32_INSTR_SLTU: begin
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valid_out <= 1;
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alu_op_out <= `RV32_ALU_OP_SLTU;
|
|
alu_sub_sra_out <= 1;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_XOR: begin
|
|
valid_out <= 1;
|
|
alu_op_out <= `RV32_ALU_OP_XOR;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_SRL: begin
|
|
valid_out <= 1;
|
|
alu_op_out <= `RV32_ALU_OP_SRL_SRA;
|
|
alu_sub_sra_out <= 0;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_SRA: begin
|
|
valid_out <= 1;
|
|
alu_op_out <= `RV32_ALU_OP_SRL_SRA;
|
|
alu_sub_sra_out <= 1;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_OR: begin
|
|
valid_out <= 1;
|
|
alu_op_out <= `RV32_ALU_OP_OR;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_AND: begin
|
|
valid_out <= 1;
|
|
alu_op_out <= `RV32_ALU_OP_AND;
|
|
alu_src1_out <= `RV32_ALU_SRC1_REG;
|
|
alu_src2_out <= `RV32_ALU_SRC2_REG;
|
|
rd_write_out <= 1;
|
|
end
|
|
`RV32_INSTR_FENCE: begin
|
|
valid_out <= 1;
|
|
end
|
|
`RV32_INSTR_FENCE_I: begin
|
|
valid_out <= 1;
|
|
end
|
|
`RV32_INSTR_ECALL: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_EBREAK: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_MRET: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_WFI: begin
|
|
valid_out <= 1;
|
|
end
|
|
`RV32_INSTR_CSRRW: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_CSRRS: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_CSRRC: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_CSRRWI: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_CSRRSI: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
`RV32_INSTR_CSRRCI: begin
|
|
valid_out <= 1;
|
|
// TODO
|
|
end
|
|
endcase
|
|
|
|
if (flush_in) begin
|
|
mem_read_out <= 0;
|
|
mem_write_out <= 0;
|
|
branch_op_out <= `RV32_BRANCH_OP_NEVER;
|
|
rd_write_out <= 0;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
`endif
|