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98 commits 1 branch 0 tags 149 KiB
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33 commits

Author SHA1 Message Date
Graham Edgecombe
a713290deb Add MRET and WFI to the decoder 
No TODO in the WFI block as it will be implemented as a no-op.
 2017-12-14 23:53:49 +00:00
Graham Edgecombe
c61234f7e4 Order ECALL/EBREAK consistently 2017-12-14 23:53:02 +00:00
Graham Edgecombe
5f84ff150b Simplify giant case statement in the decoder 
This makes it easier to add special instructions (e.g. ECALL/EBREAK)
that have unusual encodings (e.g. the funct12 field).
 2017-12-12 22:42:47 +00:00
Graham Edgecombe
d6f5bb2218 Add initial support for SYSTEM instructions to the decoder 2017-12-12 22:41:01 +00:00
Graham Edgecombe
22bce1bdeb Fix compatibility with iverilog 
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
 2017-12-09 21:03:45 +00:00
Graham Edgecombe
e801556428 Replace localparams at the root level with defines 
iverilog doesn't support localparams at the root level.
 2017-12-09 10:44:39 +00:00
Graham Edgecombe
460159a392 Rename rd_writeback to rd_write 
This is consistent with the mem_read and mem_write naming.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850 Read mem_{read,write}_en to mem_{read,write} 2017-12-07 22:37:58 +00:00
Graham Edgecombe
9541f198c2 Revert "Reset {rs1,rs2_out} when flushing the decode stage" 
This reverts commit 144cbe996fab0596230d9b7d14c94373e8e5bbba.

It isn't required as we reset the rd_writeback_out register.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
e7ae22bf31 Remove _ops.sv files 2017-12-07 22:37:58 +00:00
Graham Edgecombe
0c3b91e733 Fix load-use hazard logic 2017-12-07 22:37:58 +00:00
Graham Edgecombe
86022d42a5 Follow the standard naming/commenting conventions in hazard-related code 2017-12-07 22:37:58 +00:00
Graham Edgecombe
70d72331a7 Order outputs consistently in the decode stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
02f1d705b7 Reset {rs1,rs2_out} when flushing the decode stage 
This will prevent us needing to stall the pipeline for a load
instruction if the rs1/rs2 registers happened to match the rd register.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
eff39ad19b Add flush and stall inputs to every stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
83b7d1c9b7 Add 'from stage' comments if inputs are not from the previous stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
8e2ce65ad9 Add operand forwarding to the execute stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
acbac650bf Mark the lower 27 bits of shamt as don't care 2017-12-07 22:37:58 +00:00
Graham Edgecombe
871e1f4a32 Add LB, LBU, LH, LHU, SB and SH instructions 2017-12-07 22:37:58 +00:00
Graham Edgecombe
ee768c51d4 Add FENCE and FENCE.I instructions 
Both are currently NOPs as the implementation is currently in-order and
has separate instruction and data memories.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
88928aa1b2 Fix immediate decoding in J-type instructions 2017-12-07 22:37:58 +00:00
Graham Edgecombe
86f6e0eec1 Add branching support 2017-12-02 15:23:12 +00:00
Graham Edgecombe
4c68818134 Add writeback stage 2017-12-02 11:26:12 +00:00
Graham Edgecombe
062462eeb3 Fix indentation in rv32_decode.sv 2017-12-02 10:23:11 +00:00
Graham Edgecombe
3f8e64c65a Add memory access stage 2017-12-02 10:22:48 +00:00
Graham Edgecombe
efb33456f9 Add include guards 2017-12-01 23:30:33 +00:00
Graham Edgecombe
5884a437b8 Add JAL/JALR support to the ALU 2017-12-01 23:02:50 +00:00
Graham Edgecombe
37d703c83e Add ALU control signals to the decoder 2017-12-01 23:02:50 +00:00
Graham Edgecombe
4aa64f864a Rename valid to valid_out 2017-12-01 23:02:50 +00:00
Graham Edgecombe
30b793cbaf Add ALU 2017-12-01 23:02:50 +00:00
Graham Edgecombe
e7389a3065 Fix shamt decoding 2017-12-01 21:51:41 +00:00
Graham Edgecombe
ed238e5e9b Use -noautowire to avoid using logic in every input/output declaration 2017-12-01 18:49:48 +00:00
Graham Edgecombe
4a4dee334d Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00