Order outputs consistently in the decode stage
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1 changed files with 5 additions and 5 deletions
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@ -83,23 +83,23 @@ module rv32_decode (
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always_ff @(posedge clk) begin
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if (!stall) begin
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valid_out <= 0;
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rs1_out <= rs1;
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rs2_out <= rs2;
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rd_out <= rd;
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pc_out <= pc_in;
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valid_out <= 0;
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alu_op_out <= 4'bx;
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alu_sub_sra_out <= 1'bx;
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alu_src1_out <= 1'bx;
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alu_src2_out <= 1'bx;
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rd_writeback_out <= 0;
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mem_read_en_out <= 0;
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mem_write_en_out <= 0;
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mem_width_out <= 2'bx;
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mem_zero_extend_out <= 1'bx;
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branch_op_out <= RV32_BRANCH_OP_NEVER;
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branch_pc_src_out <= 1'bx;
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rd_out <= rd;
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rd_writeback_out <= 0;
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pc_out <= pc_in;
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imm_out <= 32'bx;
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casez ({opcode, funct3, funct7})
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