32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe e2a533babb Access data memory on negative clock edge ... This will allow shifting, sign extension and zero extension logic to be placed after reads, so we can add support for the LB, LBU, LH and LHU opcodes.		2017-12-07 22:37:58 +00:00
.gitignore	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
clk_div.sv	Add clock divider	2017-12-07 22:37:58 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
progmem.s	Use 4 space indentation in the assembly file for consistency	2017-12-07 22:37:58 +00:00
rv32.sv	Connect lower 8 bits of x31 to the LEDs for debugging	2017-12-02 15:33:45 +00:00
rv32_alu.sv	Fix ALU source multiplexers	2017-12-07 22:37:58 +00:00
rv32_alu_ops.sv	Add include guards	2017-12-01 23:30:33 +00:00
rv32_branch.sv	Ignore LSB of JALR target address	2017-12-07 22:37:58 +00:00
rv32_branch_ops.sv	Add branching support	2017-12-02 15:23:12 +00:00
rv32_decode.sv	Add FENCE and FENCE.I instructions	2017-12-07 22:37:58 +00:00
rv32_execute.sv	Replace always with always_ff	2017-12-02 18:29:51 +00:00
rv32_fetch.sv	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
rv32_mem.sv	Access data memory on negative clock edge	2017-12-07 22:37:58 +00:00
rv32_opcodes.sv	Add FENCE and FENCE.I instructions	2017-12-07 22:37:58 +00:00
rv32_regs.sv	Add include guards	2017-12-01 23:30:33 +00:00
rv32_writeback.sv	Add writeback stage	2017-12-02 11:26:12 +00:00
top.sv	Add clock divider	2017-12-07 22:37:58 +00:00
top.ys	Run abc twice to improve logic density	2017-12-07 22:37:58 +00:00