155 lines
4.9 KiB
Systemverilog
155 lines
4.9 KiB
Systemverilog
`ifndef RV32_MEM
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`define RV32_MEM
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`include "rv32_branch.sv"
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`define RV32_MEM_WIDTH_WORD 2'b00
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`define RV32_MEM_WIDTH_HALF 2'b01
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`define RV32_MEM_WIDTH_BYTE 2'b10
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module rv32_mem (
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input clk,
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/* control in (from hazard) */
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input stall_in,
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input flush_in,
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/* control in */
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input read_in,
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input write_in,
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input [1:0] width_in,
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input zero_extend_in,
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input [1:0] branch_op_in,
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input [4:0] rd_in,
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input rd_write_in,
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/* data in */
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input [31:0] result_in,
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input [31:0] rs2_value_in,
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input [31:0] branch_pc_in,
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/* data in (from memory bus) */
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input [31:0] read_value_in,
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/* control out */
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output logic branch_taken_out,
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output logic [4:0] rd_out,
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output logic rd_write_out,
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/* control out (to memory bus) */
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output logic read_out,
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output logic [3:0] write_mask_out,
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/* data out */
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output logic [31:0] rd_value_out,
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output logic [31:0] branch_pc_out,
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/* data out (to memory bus) */
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output logic [31:0] address_out,
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output logic [31:0] write_value_out
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);
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rv32_branch_unit branch_unit (
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/* control in */
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.op_in(branch_op_in),
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/* data in */
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.result_in(result_in),
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/* control out */
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.taken_out(branch_taken_out)
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);
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assign branch_pc_out = branch_pc_in;
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assign read_out = read_in;
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assign address_out = result_in;
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always_comb begin
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if (write_in) begin
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case (width_in)
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`RV32_MEM_WIDTH_WORD: begin
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write_value_out = rs2_value_in;
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write_mask_out = 4'b1111;
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end
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`RV32_MEM_WIDTH_HALF: begin
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case (result_in[0])
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2'b0: begin
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write_value_out = {rs2_value_in[15:0], 16'bx};
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write_mask_out = 4'b1100;
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end
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2'b1: begin
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write_value_out = {16'bx, rs2_value_in[15:0]};
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write_mask_out = 4'b0011;
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end
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endcase
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end
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`RV32_MEM_WIDTH_BYTE: begin
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case (result_in[1:0])
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2'b00: begin
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write_value_out = {rs2_value_in[7:0], 24'bx};
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write_mask_out = 4'b1000;
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end
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2'b01: begin
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write_value_out = {8'bx, rs2_value_in[7:0], 16'bx};
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write_mask_out = 4'b0100;
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end
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2'b10: begin
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write_value_out = {16'bx, rs2_value_in[7:0], 8'bx};
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write_mask_out = 4'b0010;
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end
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2'b11: begin
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write_value_out = {24'bx, rs2_value_in[7:0]};
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write_mask_out = 4'b0001;
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end
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endcase
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end
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default: begin
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write_value_out = 32'bx;
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write_mask_out = 4'bx;
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end
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endcase
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end else begin
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write_value_out = 32'bx;
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write_mask_out = 4'b0;
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end
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end
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always_ff @(posedge clk) begin
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if (!stall_in) begin
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rd_out <= rd_in;
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rd_write_out <= rd_write_in;
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if (read_in) begin
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case (width_in)
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`RV32_MEM_WIDTH_WORD: begin
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rd_value_out <= read_value_in;
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end
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`RV32_MEM_WIDTH_HALF: begin
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case (result_in[0])
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1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:16]};
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1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:0]};
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endcase
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end
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`RV32_MEM_WIDTH_BYTE: begin
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case (result_in[1:0])
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2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:24]};
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2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[23]}}, read_value_in[23:16]};
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2'b10: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:8]};
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2'b11: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[7]}}, read_value_in[7:0]};
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endcase
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end
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default: begin
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rd_value_out <= 32'bx;
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end
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endcase
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end else begin
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rd_value_out <= result_in;
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end
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if (flush_in)
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rd_write_out <= 0;
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end
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end
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endmodule
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`endif
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