Graham Edgecombe
f571ab29eb
Rename rv32_branch to rv32_branch_unit
2017-12-12 21:05:02 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
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This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
e801556428
Replace localparams at the root level with defines
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iverilog doesn't support localparams at the root level.
2017-12-09 10:44:39 +00:00
Graham Edgecombe
82394bce1c
Add read_out signal to the memory bus
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This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
2017-12-07 22:37:58 +00:00
Graham Edgecombe
460159a392
Rename rd_writeback to rd_write
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This is consistent with the mem_read and mem_write naming.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850
Read mem_{read,write}_en to mem_{read,write}
2017-12-07 22:37:58 +00:00
Graham Edgecombe
018faac560
Add memory bus and move data memory to a separate module
2017-12-07 22:37:58 +00:00
Graham Edgecombe
03ecd3a97d
Remove unused mem_read_en output
2017-12-07 22:37:58 +00:00
Graham Edgecombe
e7ae22bf31
Remove _ops.sv files
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0acde319b0
Stall the decode stage if it is waiting on a load
2017-12-07 22:37:58 +00:00
Graham Edgecombe
86022d42a5
Follow the standard naming/commenting conventions in hazard-related code
2017-12-07 22:37:58 +00:00
Graham Edgecombe
eff39ad19b
Add flush and stall inputs to every stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
cc89d3f93a
Replace tabs with spaces in rv32_mem.sv
2017-12-07 22:37:58 +00:00
Graham Edgecombe
dd6e01fb5c
Move result/mem_read_value mux to the mem stage
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This should reduce the logic required to forward the writeback rd_value
to the execute stage, which is on the critical path.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
871e1f4a32
Add LB, LBU, LH, LHU, SB and SH instructions
2017-12-07 22:37:58 +00:00
Graham Edgecombe
e2a533babb
Access data memory on negative clock edge
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This will allow shifting, sign extension and zero extension logic to be
placed after reads, so we can add support for the LB, LBU, LH and LHU
opcodes.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
85ba0c7faa
Remove read_value_out enable input
2017-12-07 22:37:23 +00:00
Graham Edgecombe
bef709dc73
Replace always with always_ff
2017-12-02 18:29:51 +00:00
Graham Edgecombe
86f6e0eec1
Add branching support
2017-12-02 15:23:12 +00:00
Graham Edgecombe
4c68818134
Add writeback stage
2017-12-02 11:26:12 +00:00
Graham Edgecombe
3f8e64c65a
Add memory access stage
2017-12-02 10:22:48 +00:00
