icicle/Makefile

QUIET    = -q
PLL      = pll.sv
SRC      = $(sort $(wildcard *.sv) $(PLL))
TOP      = top
SV       = $(TOP).sv
YS       = $(TOP).ys
BLIF     = $(TOP).blif
ASC_SYN  = $(TOP)_syn.asc
ASC      = $(TOP).asc
BIN      = $(TOP).bin
TIME_RPT = $(TOP).rpt
STAT     = $(TOP).stat
SPEED    = hx
DEVICE   = 8k
PACKAGE  = ct256
PCF      = ice40hx8k-b-evn.pcf
FREQ_OSC = 12
FREQ_PLL = 36
TARGET   = riscv64-unknown-elf
AS       = $(TARGET)-as
ASFLAGS  = -march=rv32i -mabi=ilp32
OBJCOPY  = $(TARGET)-objcopy

.PHONY: all clean check time stat flash

all: $(BIN)

clean:
	$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) progmem_syn.hex progmem.hex progmem.o

progmem.hex: progmem.o
	$(OBJCOPY) -O srec $< /dev/stdout \
		| srec_cat - -byte-swap 4 -output - -binary \
		| xxd -p -c 4 > $@

progmem_syn.hex:
	icebram -g 32 256 > $@

$(PLL):
	icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@

$(BLIF): $(YS) $(SRC) progmem_syn.hex
	yosys $(QUIET) -s $<

check: $(SRC) progmem_syn.hex
	iverilog -Wall -t null -g2012 `yosys-config --datdir/ice40/cells_sim.v` $(SV)

$(ASC_SYN): $(BLIF) $(PCF)
	arachne-pnr $(QUIET) -d $(DEVICE) -P $(PACKAGE) -o $@ -p $(PCF) $<

$(TIME_RPT): $(ASC_SYN) $(PCF)
	icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_PLL) -r $@ $<

$(ASC): $(ASC_SYN) progmem_syn.hex progmem.hex
	icebram progmem_syn.hex progmem.hex < $< > $@

$(BIN): $(ASC)
	icepack $< $@

time: $(TIME_RPT)
	cat $<

$(STAT): $(ASC_SYN)
	icebox_stat $< > $@

stat: $(STAT)
	cat $<

flash: $(BIN) $(TIME_RPT)
	iceprog -S $<
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`QUIET = -q`
Add PLL 2017-12-06 08:26:00 +00:00			`PLL = pll.sv`
			`SRC = $(sort $(wildcard *.sv) $(PLL))`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`TOP = top`
Add SV variable to replace $(TOP).sv 2017-12-10 14:10:33 +00:00			`SV = $(TOP).sv`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`YS = $(TOP).ys`
			`BLIF = $(TOP).blif`
Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`ASC_SYN = $(TOP)_syn.asc`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`ASC = $(TOP).asc`
			`BIN = $(TOP).bin`
Store timing report in top.rpt This stops us needing to re-generate it if the design hasn't changed. 2017-12-06 08:30:32 +00:00			`TIME_RPT = $(TOP).rpt`
Store icebox_stat output in top.stat This also takes a long time to generate. 2017-12-06 08:36:51 +00:00			`STAT = $(TOP).stat`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`SPEED = hx`
			`DEVICE = 8k`
			`PACKAGE = ct256`
			`PCF = ice40hx8k-b-evn.pcf`
			`FREQ_OSC = 12`
Add PLL 2017-12-06 08:26:00 +00:00			`FREQ_PLL = 36`
Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`TARGET = riscv64-unknown-elf`
			`AS = $(TARGET)-as`
			`ASFLAGS = -march=rv32i -mabi=ilp32`
			`OBJCOPY = $(TARGET)-objcopy`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
Add iverilog syntax check target 2017-12-09 21:33:51 +00:00			`.PHONY: all clean check time stat flash`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
Replace $(TOP).bin with $(BIN) 2017-12-10 14:10:51 +00:00			`all: $(BIN)`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
			`clean:`
Delete pll.sv in the clean target 2017-12-06 08:33:09 +00:00			`$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) progmem_syn.hex progmem.hex progmem.o`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`progmem.hex: progmem.o`
			`$(OBJCOPY) -O srec $< /dev/stdout \`
			`\| srec_cat - -byte-swap 4 -output - -binary \`
			`\| xxd -p -c 4 > $@`

			`progmem_syn.hex:`
			`icebram -g 32 256 > $@`

Add PLL 2017-12-06 08:26:00 +00:00			`$(PLL):`
			`icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@`

Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`$(BLIF): $(YS) $(SRC) progmem_syn.hex`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`yosys $(QUIET) -s $<`

Add progmem_syn.hex dependency to the check target 2017-12-10 09:25:37 +00:00			`check: $(SRC) progmem_syn.hex`
Add SV variable to replace $(TOP).sv 2017-12-10 14:10:33 +00:00			iverilog -Wall -t null -g2012 `yosys-config --datdir/ice40/cells_sim.v` $(SV)
Add iverilog syntax check target 2017-12-09 21:33:51 +00:00
Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`$(ASC_SYN): $(BLIF) $(PCF)`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`arachne-pnr $(QUIET) -d $(DEVICE) -P $(PACKAGE) -o $@ -p $(PCF) $<`

Store timing report in top.rpt This stops us needing to re-generate it if the design hasn't changed. 2017-12-06 08:30:32 +00:00			`$(TIME_RPT): $(ASC_SYN) $(PCF)`
			`icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_PLL) -r $@ $<`

Populate instr_mem with a test assembly program 2017-12-02 17:17:26 +00:00			`$(ASC): $(ASC_SYN) progmem_syn.hex progmem.hex`
			`icebram progmem_syn.hex progmem.hex < $< > $@`

Move timing closure requirement to the flash target It's possible that some tools interact with the bitstream directly rather than the .asc files, and we may still want to run them even if timing closure is not met. 2017-12-06 08:38:01 +00:00			`$(BIN): $(ASC)`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`icepack $< $@`

Store timing report in top.rpt This stops us needing to re-generate it if the design hasn't changed. 2017-12-06 08:30:32 +00:00			`time: $(TIME_RPT)`
			`cat $<`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
Store icebox_stat output in top.stat This also takes a long time to generate. 2017-12-06 08:36:51 +00:00			`$(STAT): $(ASC_SYN)`
			`icebox_stat $< > $@`

			`stat: $(STAT)`
			`cat $<`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00
Move timing closure requirement to the flash target It's possible that some tools interact with the bitstream directly rather than the .asc files, and we may still want to run them even if timing closure is not met. 2017-12-06 08:38:01 +00:00			`flash: $(BIN) $(TIME_RPT)`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`iceprog -S $<`