32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 04dc25c5dc Merge memory bus inputs/outputs in the port list ... I don't think the control/data in/out split makes as much sense - it's a convention much better suited to the pipeline stages.		2017-12-12 21:15:11 +00:00
.gitignore	Store icebox_stat output in top.stat	2017-12-07 22:37:58 +00:00
clk_div.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Replace $(TOP).bin with $(BIN)	2017-12-10 14:10:51 +00:00
progmem.s	Add UART demo program	2017-12-07 22:37:59 +00:00
ram.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00
rv32.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00
rv32_alu.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
rv32_branch.sv	Rename rv32_branch to rv32_branch_unit	2017-12-12 21:05:02 +00:00
rv32_decode.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
rv32_execute.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
rv32_fetch.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
rv32_hazard.sv	Rename rv32_hazard to rv32_hazard_unit	2017-12-12 21:04:33 +00:00
rv32_mem.sv	Rename rv32_branch to rv32_branch_unit	2017-12-12 21:05:02 +00:00
rv32_opcodes.sv	Replace localparams at the root level with defines	2017-12-09 10:44:39 +00:00
rv32_regs.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
sync.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
top.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00
top.ys	Pass -full to opt	2017-12-08 22:29:22 +00:00
uart.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00