04dc25c5dc
I don't think the control/data in/out split makes as much sense - it's a convention much better suited to the pipeline stages.
275 lines
7.1 KiB
Systemverilog
275 lines
7.1 KiB
Systemverilog
`ifndef RV32
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`define RV32
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`include "rv32_decode.sv"
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`include "rv32_execute.sv"
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`include "rv32_fetch.sv"
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`include "rv32_hazard.sv"
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`include "rv32_mem.sv"
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module rv32 (
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input clk,
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/* memory bus */
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output logic [31:0] address_out,
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output logic read_out,
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input [31:0] read_value_in,
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output logic [3:0] write_mask_out,
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output logic [31:0] write_value_out
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);
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/* hazard -> fetch control */
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logic fetch_stall;
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logic fetch_flush;
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/* hazard -> decode control */
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logic decode_stall;
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logic decode_flush;
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/* hazard -> execute control */
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logic execute_stall;
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logic execute_flush;
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/* hazard -> mem control */
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logic mem_stall;
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logic mem_flush;
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/* fetch -> decode data */
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logic [31:0] fetch_pc;
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logic [31:0] fetch_instr;
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/* decode -> hazard control */
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logic [4:0] decode_rs1_unreg;
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logic [4:0] decode_rs2_unreg;
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/* decode -> execute control */
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logic [4:0] decode_rs1;
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logic [4:0] decode_rs2;
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logic [3:0] decode_alu_op;
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logic decode_alu_sub_sra;
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logic decode_alu_src1;
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logic decode_alu_src2;
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logic decode_mem_read;
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logic decode_mem_write;
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logic [1:0] decode_mem_width;
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logic decode_mem_zero_extend;
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logic [1:0] decode_branch_op;
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logic decode_branch_pc_src;
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logic [4:0] decode_rd;
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logic decode_rd_write;
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/* decode -> execute data */
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logic [31:0] decode_pc;
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logic [31:0] decode_rs1_value;
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logic [31:0] decode_rs2_value;
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logic [31:0] decode_imm;
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/* execute -> mem control */
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logic execute_mem_read;
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logic execute_mem_write;
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logic [1:0] execute_mem_width;
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logic execute_mem_zero_extend;
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logic [1:0] execute_branch_op;
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logic [4:0] execute_rd;
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logic execute_rd_write;
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/* execute -> mem data */
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logic [31:0] execute_result;
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logic [31:0] execute_rs2_value;
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logic [31:0] execute_branch_pc;
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/* mem -> writeback control */
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logic [4:0] mem_rd;
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logic mem_rd_write;
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/* mem -> fetch control */
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logic mem_branch_taken;
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/* mem -> writeback data */
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logic [31:0] mem_rd_value;
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/* mem -> fetch data */
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logic [31:0] mem_branch_pc;
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rv32_hazard_unit hazard_unit (
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/* control in */
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.decode_rs1_in(decode_rs1_unreg),
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.decode_rs2_in(decode_rs2_unreg),
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.decode_mem_read_in(decode_mem_read),
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.decode_rd_in(decode_rd),
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.decode_rd_write_in(decode_rd_write),
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.mem_branch_taken_in(mem_branch_taken),
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/* control out */
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.fetch_stall_out(fetch_stall),
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.fetch_flush_out(fetch_flush),
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.decode_stall_out(decode_stall),
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.decode_flush_out(decode_flush),
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.execute_stall_out(execute_stall),
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.execute_flush_out(execute_flush),
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.mem_stall_out(mem_stall),
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.mem_flush_out(mem_flush)
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);
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rv32_fetch fetch (
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.clk(clk),
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/* control in (from hazard) */
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.stall_in(fetch_stall),
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.flush_in(fetch_flush),
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/* control in (from mem) */
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.branch_taken_in(mem_branch_taken),
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/* data in (from mem) */
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.branch_pc_in(mem_branch_pc),
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/* data out */
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.pc_out(fetch_pc),
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.instr_out(fetch_instr)
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);
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rv32_decode decode (
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.clk(clk),
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/* control in (from hazard) */
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.stall_in(decode_stall),
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.flush_in(decode_flush),
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/* control in (from writeback) */
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.rd_in(mem_rd),
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.rd_write_in(mem_rd_write),
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/* data in */
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.pc_in(fetch_pc),
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.instr_in(fetch_instr),
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/* data in (from writeback) */
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.rd_value_in(mem_rd_value),
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/* control out (to hazard) */
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.rs1_unreg_out(decode_rs1_unreg),
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.rs2_unreg_out(decode_rs2_unreg),
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/* control out */
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.rs1_out(decode_rs1),
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.rs2_out(decode_rs2),
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.alu_op_out(decode_alu_op),
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.alu_sub_sra_out(decode_alu_sub_sra),
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.alu_src1_out(decode_alu_src1),
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.alu_src2_out(decode_alu_src2),
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.mem_read_out(decode_mem_read),
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.mem_write_out(decode_mem_write),
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.mem_width_out(decode_mem_width),
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.mem_zero_extend_out(decode_mem_zero_extend),
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.branch_op_out(decode_branch_op),
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.branch_pc_src_out(decode_branch_pc_src),
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.rd_out(decode_rd),
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.rd_write_out(decode_rd_write),
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/* data out */
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.pc_out(decode_pc),
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.rs1_value_out(decode_rs1_value),
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.rs2_value_out(decode_rs2_value),
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.imm_out(decode_imm)
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);
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rv32_execute execute (
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.clk(clk),
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/* control in (from hazard) */
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.stall_in(execute_stall),
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.flush_in(execute_flush),
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/* control in */
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.rs1_in(decode_rs1),
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.rs2_in(decode_rs2),
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.alu_op_in(decode_alu_op),
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.alu_sub_sra_in(decode_alu_sub_sra),
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.alu_src1_in(decode_alu_src1),
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.alu_src2_in(decode_alu_src2),
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.mem_read_in(decode_mem_read),
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.mem_write_in(decode_mem_write),
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.mem_width_in(decode_mem_width),
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.mem_zero_extend_in(decode_mem_zero_extend),
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.branch_op_in(decode_branch_op),
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.branch_pc_src_in(decode_branch_pc_src),
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.rd_in(decode_rd),
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.rd_write_in(decode_rd_write),
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/* control in (from writeback) */
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.writeback_rd_in(mem_rd),
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.writeback_rd_write_in(mem_rd_write),
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/* data in */
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.pc_in(decode_pc),
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.rs1_value_in(decode_rs1_value),
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.rs2_value_in(decode_rs2_value),
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.imm_in(decode_imm),
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/* data in (from writeback) */
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.writeback_rd_value_in(mem_rd_value),
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/* control out */
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.mem_read_out(execute_mem_read),
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.mem_write_out(execute_mem_write),
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.mem_width_out(execute_mem_width),
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.mem_zero_extend_out(execute_mem_zero_extend),
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.branch_op_out(execute_branch_op),
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.rd_out(execute_rd),
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.rd_write_out(execute_rd_write),
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/* data out */
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.result_out(execute_result),
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.rs2_value_out(execute_rs2_value),
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.branch_pc_out(execute_branch_pc)
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);
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rv32_mem mem (
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.clk(clk),
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/* control in (from hazard) */
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.stall_in(mem_stall),
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.flush_in(mem_flush),
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/* control in */
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.read_in(execute_mem_read),
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.write_in(execute_mem_write),
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.width_in(execute_mem_width),
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.zero_extend_in(execute_mem_zero_extend),
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.branch_op_in(execute_branch_op),
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.rd_in(execute_rd),
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.rd_write_in(execute_rd_write),
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/* data in */
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.result_in(execute_result),
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.rs2_value_in(execute_rs2_value),
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.branch_pc_in(execute_branch_pc),
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/* data in (from memory bus) */
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.read_value_in(read_value_in),
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/* control out */
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.branch_taken_out(mem_branch_taken),
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.rd_out(mem_rd),
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.rd_write_out(mem_rd_write),
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/* control out (to memory bus) */
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.read_out(read_out),
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.write_mask_out(write_mask_out),
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/* data out */
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.rd_value_out(mem_rd_value),
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.branch_pc_out(mem_branch_pc),
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/* data out (to memory bus) */
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.address_out(address_out),
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.write_value_out(write_value_out)
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);
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endmodule
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`endif
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