Graham Edgecombe
04dc25c5dc
Merge memory bus inputs/outputs in the port list
...
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
2017-12-12 21:15:11 +00:00
Graham Edgecombe
58ff5c9ec7
Rename rv32_hazard to rv32_hazard_unit
2017-12-12 21:04:33 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
82394bce1c
Add read_out signal to the memory bus
...
This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
2017-12-07 22:37:58 +00:00
Graham Edgecombe
460159a392
Rename rd_writeback to rd_write
...
This is consistent with the mem_read and mem_write naming.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850
Read mem_{read,write}_en to mem_{read,write}
2017-12-07 22:37:58 +00:00
Graham Edgecombe
365d3e37c6
Memory map the LEDs
2017-12-07 22:37:58 +00:00
Graham Edgecombe
018faac560
Add memory bus and move data memory to a separate module
2017-12-07 22:37:58 +00:00
Graham Edgecombe
03ecd3a97d
Remove unused mem_read_en output
2017-12-07 22:37:58 +00:00
Graham Edgecombe
da26f86f25
Remove two cycle load-use stall
...
There's no need for it as we forward results from the writeback to the
execute stage.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0c3b91e733
Fix load-use hazard logic
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0acde319b0
Stall the decode stage if it is waiting on a load
2017-12-07 22:37:58 +00:00
Graham Edgecombe
965311c1e5
Add mem_ prefix to the hazard unit's branch_taken input
2017-12-07 22:37:58 +00:00
Graham Edgecombe
86022d42a5
Follow the standard naming/commenting conventions in hazard-related code
2017-12-07 22:37:58 +00:00
Graham Edgecombe
5ec95c00a2
Flush the decode/execute stages if a branch is taken
2017-12-07 22:37:58 +00:00
Graham Edgecombe
4c2c44e94d
Add initial hazard unit
2017-12-07 22:37:58 +00:00
Graham Edgecombe
310c275ba2
Hard-wire stall and flush inputs to zero
2017-12-07 22:37:58 +00:00
Graham Edgecombe
83b7d1c9b7
Add 'from stage' comments if inputs are not from the previous stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
dd6e01fb5c
Move result/mem_read_value mux to the mem stage
...
This should reduce the logic required to forward the writeback rd_value
to the execute stage, which is on the critical path.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
8e2ce65ad9
Add operand forwarding to the execute stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
871e1f4a32
Add LB, LBU, LH, LHU, SB and SH instructions
2017-12-07 22:37:58 +00:00
Graham Edgecombe
9de9955ad0
Connect lower 8 bits of x31 to the LEDs for debugging
2017-12-02 15:33:45 +00:00
Graham Edgecombe
86f6e0eec1
Add branching support
2017-12-02 15:23:12 +00:00
Graham Edgecombe
4c68818134
Add writeback stage
2017-12-02 11:26:12 +00:00
Graham Edgecombe
3f8e64c65a
Add memory access stage
2017-12-02 10:22:48 +00:00
Graham Edgecombe
efb33456f9
Add include guards
2017-12-01 23:30:33 +00:00
Graham Edgecombe
30b793cbaf
Add ALU
2017-12-01 23:02:50 +00:00
Graham Edgecombe
ed238e5e9b
Use -noautowire to avoid using logic in every input/output declaration
2017-12-01 18:49:48 +00:00
Graham Edgecombe
4a4dee334d
Add initial fetch/decode stages
2017-12-01 08:46:43 +00:00
