icicle/top.ys

read_verilog -noautowire -sv top.sv
proc
opt -full
alumacc
share -aggressive
synth_ice40 -abc2 -top top -blif top.blif
Use -noautowire to avoid using logic in every input/output declaration 2017-12-01 18:45:47 +00:00			`read_verilog -noautowire -sv top.sv`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`proc`
Pass -full to opt Reduces the number of LUTs slightly. 2017-12-08 22:29:22 +00:00			`opt -full`
Add initial fetch/decode stages 2017-11-30 22:30:49 +00:00			`alumacc`
			`share -aggressive`
Run abc twice to improve logic density 2017-12-02 19:23:23 +00:00			`synth_ice40 -abc2 -top top -blif top.blif`