17 lines
327 B
Systemverilog
17 lines
327 B
Systemverilog
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module rv32_fetch (
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input logic clk,
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/* data out */
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output logic [31:0] pc_out,
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output logic [31:0] instr_out
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);
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logic [31:0] instr_mem [255:0];
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logic [31:0] pc;
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always_ff @(posedge clk) begin
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instr_out <= instr_mem[pc[31:2]];
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pc <= pc + 4;
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pc_out <= pc;
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end
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endmodule
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