Merge memory bus inputs/outputs in the port list

I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.

ram.sv

@@ -4,16 +4,12 @@
 module ram (
     input clk,
 
-    /* control in */
+    /* memory bus */
-    input sel_in,
-    input [3:0] write_mask_in,
-
-    /* data in */
     input [31:0] address_in,
-    input [31:0] write_value_in,
+    input sel_in,
-
+    output logic [31:0] read_value_out,
-    /* data out */
+    input [3:0] write_mask_in,
-    output logic [31:0] read_value_out
+    input [31:0] write_value_in
 );
     logic [31:0] mem [2047:0];
     logic [31:0] read_value;

rv32.sv

@@ -10,15 +10,11 @@
 module rv32 (
     input clk,
 
-    /* control out (memory bus) */
+    /* memory bus */
-    output logic read_out,
-    output logic [3:0] write_mask_out,
-
-    /* data in (memory bus) */
-    input [31:0] read_value_in,
-
-    /* data out (memory bus) */
     output logic [31:0] address_out,
+    output logic read_out,
+    input [31:0] read_value_in,
+    output logic [3:0] write_mask_out,
     output logic [31:0] write_value_out
 );
     /* hazard -> fetch control */

top.sv

@@ -58,13 +58,11 @@ module top (
         .out(pll_locked)
     );
 
-    /* memory bus control */
+    /* memory bus */
-    logic mem_read;
-    logic [3:0] mem_write_mask;
-
-    /* memory bus data */
     logic [31:0] mem_address;
+    logic mem_read;
     logic [31:0] mem_read_value;
+    logic [3:0] mem_write_mask;
     logic [31:0] mem_write_value;
 
     assign mem_read_value = ram_read_value | leds_read_value | uart_read_value;
@@ -72,15 +70,11 @@ module top (
     rv32 rv32 (
         .clk(pll_clk),
 
-        /* control out */
+        /* memory bus */
-        .read_out(mem_read),
-        .write_mask_out(mem_write_mask),
-
-        /* data in */
-        .read_value_in(mem_read_value),
-
-        /* data out */
         .address_out(mem_address),
+        .read_out(mem_read),
+        .read_value_in(mem_read_value),
+        .write_mask_out(mem_write_mask),
         .write_value_out(mem_write_value)
     );
 
@@ -102,16 +96,12 @@ module top (
     ram ram (
         .clk(pll_clk),
 
-        /* control in */
+        /* memory bus */
-        .sel_in(ram_sel),
-        .write_mask_in(mem_write_mask),
-
-        /* data in */
         .address_in(mem_address),
-        .write_value_in(mem_write_value),
+        .sel_in(ram_sel),
-
+        .read_value_out(ram_read_value),
-        /* data out */
+        .write_mask_in(mem_write_mask),
-        .read_value_out(ram_read_value)
+        .write_value_in(mem_write_value)
     );
 
     logic leds_sel;
@@ -135,16 +125,12 @@ module top (
         .rx_in(uart_rx),
         .tx_out(uart_tx),
 
-        /* control in */
+        /* memory bus */
+        .address_in(mem_address),
         .sel_in(uart_sel),
         .read_in(mem_read),
+        .read_value_out(uart_read_value),
         .write_mask_in(mem_write_mask),
-
+        .write_value_in(mem_write_value)
-        /* data in */
-        .address_in(mem_address),
-        .write_value_in(mem_write_value),
-
-        /* data out */
-        .read_value_out(uart_read_value)
     );
 endmodule

uart.sv

@@ -13,17 +13,13 @@ module uart (
     input rx_in,
     output logic tx_out,
 
-    /* control in */
+    /* memory bus */
+    input [31:0] address_in,
     input sel_in,
     input read_in,
+    output logic [31:0] read_value_out,
     input [3:0] write_mask_in,
-
+    input [31:0] write_value_in
-    /* data in */
-    input [31:0] address_in,
-    input [31:0] write_value_in,
-
-    /* data out */
-    output logic [31:0] read_value_out
 );
     logic [15:0] clk_div;