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Replace localparams at the root level with defines

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iverilog doesn't support localparams at the root level.
This commit is contained in:
Graham Edgecombe 2017-12-09 10:44:39 +00:00
parent bf7b1bef4f
commit e801556428
8 changed files with 269 additions and 269 deletions
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50
rv32_alu.sv
View file

@ -1,22 +1,22 @@
`ifndef RV32_ALU `ifndef RV32_ALU
`define RV32_ALU `define RV32_ALU
localparam RV32_ALU_OP_ADD_SUB = 4'b0000; `define RV32_ALU_OP_ADD_SUB 4'b0000
localparam RV32_ALU_OP_XOR = 4'b0001; `define RV32_ALU_OP_XOR 4'b0001
localparam RV32_ALU_OP_OR = 4'b0010; `define RV32_ALU_OP_OR 4'b0010
localparam RV32_ALU_OP_AND = 4'b0011; `define RV32_ALU_OP_AND 4'b0011
localparam RV32_ALU_OP_SLL = 4'b0100; `define RV32_ALU_OP_SLL 4'b0100
localparam RV32_ALU_OP_SRL_SRA = 4'b0101; `define RV32_ALU_OP_SRL_SRA 4'b0101
localparam RV32_ALU_OP_SLT = 4'b0110; `define RV32_ALU_OP_SLT 4'b0110
localparam RV32_ALU_OP_SLTU = 4'b0111; `define RV32_ALU_OP_SLTU 4'b0111
localparam RV32_ALU_OP_SRC1P4 = 4'b1000; `define RV32_ALU_OP_SRC1P4 4'b1000
localparam RV32_ALU_OP_SRC2 = 4'b1001; `define RV32_ALU_OP_SRC2 4'b1001
localparam RV32_ALU_SRC1_REG = 1'b0; `define RV32_ALU_SRC1_REG 1'b0
localparam RV32_ALU_SRC1_PC = 1'b1; `define RV32_ALU_SRC1_PC 1'b1
localparam RV32_ALU_SRC2_REG = 1'b0; `define RV32_ALU_SRC2_REG 1'b0
localparam RV32_ALU_SRC2_IMM = 1'b1; `define RV32_ALU_SRC2_IMM 1'b1
module rv32_alu ( module rv32_alu (
/* control in */ /* control in */
@ -54,17 +54,17 @@ module rv32_alu (
always_comb begin always_comb begin
case (op_in) case (op_in)
RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0]; `RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0];
RV32_ALU_OP_XOR: result_out = src1 ^ src2; `RV32_ALU_OP_XOR: result_out = src1 ^ src2;
RV32_ALU_OP_OR: result_out = src1 | src2; `RV32_ALU_OP_OR: result_out = src1 | src2;
RV32_ALU_OP_AND: result_out = src1 & src2; `RV32_ALU_OP_AND: result_out = src1 & src2;
RV32_ALU_OP_SLL: result_out = src1 << shamt; `RV32_ALU_OP_SLL: result_out = src1 << shamt;
RV32_ALU_OP_SRL_SRA: result_out = srl_sra; `RV32_ALU_OP_SRL_SRA: result_out = srl_sra;
RV32_ALU_OP_SLT: result_out = {31'b0, lt}; `RV32_ALU_OP_SLT: result_out = {31'b0, lt};
RV32_ALU_OP_SLTU: result_out = {31'b0, ltu}; `RV32_ALU_OP_SLTU: result_out = {31'b0, ltu};
RV32_ALU_OP_SRC1P4: result_out = src1 + 4; `RV32_ALU_OP_SRC1P4: result_out = src1 + 4;
RV32_ALU_OP_SRC2: result_out = src2; `RV32_ALU_OP_SRC2: result_out = src2;
default: result_out = 32'bx; default: result_out = 32'bx;
endcase endcase
end end
endmodule endmodule

20
rv32_branch.sv
View file

@ -1,13 +1,13 @@
`ifndef RV32_BRANCH `ifndef RV32_BRANCH
`define RV32_BRANCH `define RV32_BRANCH
localparam RV32_BRANCH_OP_NEVER = 3'b00; `define RV32_BRANCH_OP_NEVER 3'b00
localparam RV32_BRANCH_OP_ZERO = 3'b01; `define RV32_BRANCH_OP_ZERO 3'b01
localparam RV32_BRANCH_OP_NON_ZERO = 3'b10; `define RV32_BRANCH_OP_NON_ZERO 3'b10
localparam RV32_BRANCH_OP_ALWAYS = 3'b11; `define RV32_BRANCH_OP_ALWAYS 3'b11
localparam RV32_BRANCH_PC_SRC_IMM = 1'b0; `define RV32_BRANCH_PC_SRC_IMM 1'b0
localparam RV32_BRANCH_PC_SRC_REG = 1'b1; `define RV32_BRANCH_PC_SRC_REG 1'b1
module rv32_branch_pc_mux ( module rv32_branch_pc_mux (
/* control in */ /* control in */
@ -40,10 +40,10 @@ module rv32_branch (
always_comb begin always_comb begin
case (op_in) case (op_in)
RV32_BRANCH_OP_NEVER: taken_out = 0; `RV32_BRANCH_OP_NEVER: taken_out = 0;
RV32_BRANCH_OP_ZERO: taken_out = ~non_zero; `RV32_BRANCH_OP_ZERO: taken_out = ~non_zero;
RV32_BRANCH_OP_NON_ZERO: taken_out = non_zero; `RV32_BRANCH_OP_NON_ZERO: taken_out = non_zero;
RV32_BRANCH_OP_ALWAYS: taken_out = 1; `RV32_BRANCH_OP_ALWAYS: taken_out = 1;
endcase endcase
end end
endmodule endmodule

346
rv32_decode.sv
View file

@ -103,7 +103,7 @@ module rv32_decode (
mem_write_out <= 0; mem_write_out <= 0;
mem_width_out <= 2'bx; mem_width_out <= 2'bx;
mem_zero_extend_out <= 1'bx; mem_zero_extend_out <= 1'bx;
branch_op_out <= RV32_BRANCH_OP_NEVER; branch_op_out <= `RV32_BRANCH_OP_NEVER;
branch_pc_src_out <= 1'bx; branch_pc_src_out <= 1'bx;
rd_out <= rd; rd_out <= rd;
rd_write_out <= 0; rd_write_out <= 0;
@ -112,384 +112,384 @@ module rv32_decode (
imm_out <= 32'bx; imm_out <= 32'bx;
casez ({opcode, funct3, funct7}) casez ({opcode, funct3, funct7})
{RV32_OPCODE_LUI, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LUI, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin
/* LUI */ /* LUI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRC2; alu_op_out <= `RV32_ALU_OP_SRC2;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_u; imm_out <= imm_u;
end end
{RV32_OPCODE_AUIPC, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_AUIPC, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin
/* AUIPC */ /* AUIPC */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_PC; alu_src1_out <= `RV32_ALU_SRC1_PC;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_u; imm_out <= imm_u;
end end
{RV32_OPCODE_JAL, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_JAL, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin
/* JAL */ /* JAL */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRC1P4; alu_op_out <= `RV32_ALU_OP_SRC1P4;
alu_src1_out <= RV32_ALU_SRC1_PC; alu_src1_out <= `RV32_ALU_SRC1_PC;
branch_op_out <= RV32_BRANCH_OP_ALWAYS; branch_op_out <= `RV32_BRANCH_OP_ALWAYS;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_j; imm_out <= imm_j;
end end
{RV32_OPCODE_JALR, RV32_FUNCT3_ZERO, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_JALR, `RV32_FUNCT3_ZERO, `RV32_FUNCT7_ANY}: begin
/* JALR */ /* JALR */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRC1P4; alu_op_out <= `RV32_ALU_OP_SRC1P4;
alu_src1_out <= RV32_ALU_SRC1_PC; alu_src1_out <= `RV32_ALU_SRC1_PC;
branch_op_out <= RV32_BRANCH_OP_ALWAYS; branch_op_out <= `RV32_BRANCH_OP_ALWAYS;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_REG; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_REG;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BEQ, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BEQ, `RV32_FUNCT7_ANY}: begin
/* BEQ */ /* BEQ */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_ZERO; branch_op_out <= `RV32_BRANCH_OP_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BNE, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BNE, `RV32_FUNCT7_ANY}: begin
/* BNE */ /* BNE */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_NON_ZERO; branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLT, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BLT, `RV32_FUNCT7_ANY}: begin
/* BLT */ /* BLT */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLT; alu_op_out <= `RV32_ALU_OP_SLT;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_NON_ZERO; branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGE, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BGE, `RV32_FUNCT7_ANY}: begin
/* BGE */ /* BGE */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLT; alu_op_out <= `RV32_ALU_OP_SLT;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_ZERO; branch_op_out <= `RV32_BRANCH_OP_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLTU, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BLTU, `RV32_FUNCT7_ANY}: begin
/* BLTU */ /* BLTU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLTU; alu_op_out <= `RV32_ALU_OP_SLTU;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_NON_ZERO; branch_op_out <= `RV32_BRANCH_OP_NON_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGEU, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BGEU, `RV32_FUNCT7_ANY}: begin
/* BGEU */ /* BGEU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLTU; alu_op_out <= `RV32_ALU_OP_SLTU;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
branch_op_out <= RV32_BRANCH_OP_ZERO; branch_op_out <= `RV32_BRANCH_OP_ZERO;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM;
imm_out <= imm_b; imm_out <= imm_b;
end end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LB, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LB, `RV32_FUNCT7_ANY}: begin
/* LB */ /* LB */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_read_out <= 1; mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_BYTE; mem_width_out <= `RV32_MEM_WIDTH_BYTE;
mem_zero_extend_out <= 0; mem_zero_extend_out <= 0;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LH, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LH, `RV32_FUNCT7_ANY}: begin
/* LH */ /* LH */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_read_out <= 1; mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_HALF; mem_width_out <= `RV32_MEM_WIDTH_HALF;
mem_zero_extend_out <= 0; mem_zero_extend_out <= 0;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LW, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LW, `RV32_FUNCT7_ANY}: begin
/* LW */ /* LW */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_read_out <= 1; mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_WORD; mem_width_out <= `RV32_MEM_WIDTH_WORD;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LBU, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LBU, `RV32_FUNCT7_ANY}: begin
/* LBU */ /* LBU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_read_out <= 1; mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_BYTE; mem_width_out <= `RV32_MEM_WIDTH_BYTE;
mem_zero_extend_out <= 1; mem_zero_extend_out <= 1;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LHU, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LHU, `RV32_FUNCT7_ANY}: begin
/* LHU */ /* LHU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_read_out <= 1; mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_HALF; mem_width_out <= `RV32_MEM_WIDTH_HALF;
mem_zero_extend_out <= 1; mem_zero_extend_out <= 1;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SB, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SB, `RV32_FUNCT7_ANY}: begin
/* SB */ /* SB */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_write_out <= 1; mem_write_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_BYTE; mem_width_out <= `RV32_MEM_WIDTH_BYTE;
imm_out <= imm_s; imm_out <= imm_s;
end end
{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SH, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SH, `RV32_FUNCT7_ANY}: begin
/* SH */ /* SH */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_write_out <= 1; mem_write_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_HALF; mem_width_out <= `RV32_MEM_WIDTH_HALF;
imm_out <= imm_s; imm_out <= imm_s;
end end
{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SW, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SW, `RV32_FUNCT7_ANY}: begin
/* SW */ /* SW */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
mem_write_out <= 1; mem_write_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_WORD; mem_width_out <= `RV32_MEM_WIDTH_WORD;
imm_out <= imm_s; imm_out <= imm_s;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_ANY}: begin
/* ADDI */ /* ADDI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLT, `RV32_FUNCT7_ANY}: begin
/* SLTI */ /* SLTI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLT; alu_op_out <= `RV32_ALU_OP_SLT;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLTU, `RV32_FUNCT7_ANY}: begin
/* SLTIU */ /* SLTIU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLTU; alu_op_out <= `RV32_ALU_OP_SLTU;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_XOR, `RV32_FUNCT7_ANY}: begin
/* XORI */ /* XORI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_XOR; alu_op_out <= `RV32_ALU_OP_XOR;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_OR, `RV32_FUNCT7_ANY}: begin
/* ORI */ /* ORI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_OR; alu_op_out <= `RV32_ALU_OP_OR;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_AND, `RV32_FUNCT7_ANY}: begin
/* ANDI */ /* ANDI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_AND; alu_op_out <= `RV32_ALU_OP_AND;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= imm_i; imm_out <= imm_i;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLL, `RV32_FUNCT7_ZERO}: begin
/* SLLI */ /* SLLI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLL; alu_op_out <= `RV32_ALU_OP_SLL;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= shamt; imm_out <= shamt;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_ZERO}: begin
/* SRLI */ /* SRLI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRL_SRA; alu_op_out <= `RV32_ALU_OP_SRL_SRA;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= shamt; imm_out <= shamt;
end end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_OP_SRA}: begin
/* SRAI */ /* SRAI */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRL_SRA; alu_op_out <= `RV32_ALU_OP_SRL_SRA;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM; alu_src2_out <= `RV32_ALU_SRC2_IMM;
rd_write_out <= 1; rd_write_out <= 1;
imm_out <= shamt; imm_out <= shamt;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_ZERO}: begin
/* ADD */ /* ADD */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_OP_SUB}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_OP_SUB}: begin
/* SUB */ /* SUB */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_ADD_SUB; alu_op_out <= `RV32_ALU_OP_ADD_SUB;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLL, `RV32_FUNCT7_ZERO}: begin
/* SLL */ /* SLL */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLL; alu_op_out <= `RV32_ALU_OP_SLL;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLT, `RV32_FUNCT7_ZERO}: begin
/* SLT */ /* SLT */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLT; alu_op_out <= `RV32_ALU_OP_SLT;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLTU, `RV32_FUNCT7_ZERO}: begin
/* SLTU */ /* SLTU */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SLTU; alu_op_out <= `RV32_ALU_OP_SLTU;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_XOR, `RV32_FUNCT7_ZERO}: begin
/* XOR */ /* XOR */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_XOR; alu_op_out <= `RV32_ALU_OP_XOR;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_ZERO}: begin
/* SRL */ /* SRL */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRL_SRA; alu_op_out <= `RV32_ALU_OP_SRL_SRA;
alu_sub_sra_out <= 0; alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_OP_SRA}: begin
/* SRA */ /* SRA */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRL_SRA; alu_op_out <= `RV32_ALU_OP_SRL_SRA;
alu_sub_sra_out <= 1; alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_OR, `RV32_FUNCT7_ZERO}: begin
/* OR */ /* OR */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_OR; alu_op_out <= `RV32_ALU_OP_OR;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ZERO}: begin {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_AND, `RV32_FUNCT7_ZERO}: begin
/* AND */ /* AND */
valid_out <= 1; valid_out <= 1;
alu_op_out <= RV32_ALU_OP_AND; alu_op_out <= `RV32_ALU_OP_AND;
alu_src1_out <= RV32_ALU_SRC1_REG; alu_src1_out <= `RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG; alu_src2_out <= `RV32_ALU_SRC2_REG;
rd_write_out <= 1; rd_write_out <= 1;
end end
{RV32_OPCODE_MISC_MEM, RV32_FUNCT3_MISC_MEM_FENCE, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_MISC_MEM, `RV32_FUNCT3_MISC_MEM_FENCE, `RV32_FUNCT7_ANY}: begin
/* FENCE */ /* FENCE */
valid_out <= 1; valid_out <= 1;
end end
{RV32_OPCODE_MISC_MEM, RV32_FUNCT3_MISC_MEM_FENCE_I, RV32_FUNCT7_ANY}: begin {`RV32_OPCODE_MISC_MEM, `RV32_FUNCT3_MISC_MEM_FENCE_I, `RV32_FUNCT7_ANY}: begin
/* FENCE.I */ /* FENCE.I */
valid_out <= 1; valid_out <= 1;
end end
@ -498,7 +498,7 @@ module rv32_decode (
if (flush_in) begin if (flush_in) begin
mem_read_out <= 0; mem_read_out <= 0;
mem_write_out <= 0; mem_write_out <= 0;
branch_op_out <= RV32_BRANCH_OP_NEVER; branch_op_out <= `RV32_BRANCH_OP_NEVER;
rd_write_out <= 0; rd_write_out <= 0;
end end
end end

2
rv32_execute.sv
View file

@ -123,7 +123,7 @@ module rv32_execute (
if (flush_in) begin if (flush_in) begin
mem_read_out <= 0; mem_read_out <= 0;
mem_write_out <= 0; mem_write_out <= 0;
branch_op_out <= RV32_BRANCH_OP_NEVER; branch_op_out <= `RV32_BRANCH_OP_NEVER;
rd_write_out <= 0; rd_write_out <= 0;
end end
end end

2
rv32_fetch.sv
View file

@ -35,7 +35,7 @@ module rv32_fetch (
pc_out <= pc; pc_out <= pc;
if (flush_in) if (flush_in)
instr_out <= RV32_INSTR_NOP; instr_out <= `RV32_INSTR_NOP;
end end
end end
endmodule endmodule

18
rv32_mem.sv
View file

@ -3,9 +3,9 @@
`include "rv32_branch.sv" `include "rv32_branch.sv"
localparam RV32_MEM_WIDTH_WORD = 2'b00; `define RV32_MEM_WIDTH_WORD 2'b00
localparam RV32_MEM_WIDTH_HALF = 2'b01; `define RV32_MEM_WIDTH_HALF 2'b01
localparam RV32_MEM_WIDTH_BYTE = 2'b10; `define RV32_MEM_WIDTH_BYTE 2'b10
module rv32_mem ( module rv32_mem (
input clk, input clk,
@ -67,11 +67,11 @@ module rv32_mem (
always_comb begin always_comb begin
if (write_in) begin if (write_in) begin
case (width_in) case (width_in)
RV32_MEM_WIDTH_WORD: begin `RV32_MEM_WIDTH_WORD: begin
write_value_out = rs2_value_in; write_value_out = rs2_value_in;
write_mask_out = 4'b1111; write_mask_out = 4'b1111;
end end
RV32_MEM_WIDTH_HALF: begin `RV32_MEM_WIDTH_HALF: begin
case (result_in[0]) case (result_in[0])
2'b0: begin 2'b0: begin
write_value_out = {rs2_value_in[15:0], 16'bx}; write_value_out = {rs2_value_in[15:0], 16'bx};
@ -83,7 +83,7 @@ module rv32_mem (
end end
endcase endcase
end end
RV32_MEM_WIDTH_BYTE: begin `RV32_MEM_WIDTH_BYTE: begin
case (result_in[1:0]) case (result_in[1:0])
2'b00: begin 2'b00: begin
write_value_out = {rs2_value_in[7:0], 24'bx}; write_value_out = {rs2_value_in[7:0], 24'bx};
@ -121,16 +121,16 @@ module rv32_mem (
if (read_in) begin if (read_in) begin
case (width_in) case (width_in)
RV32_MEM_WIDTH_WORD: begin `RV32_MEM_WIDTH_WORD: begin
rd_value_out <= read_value_in; rd_value_out <= read_value_in;
end end
RV32_MEM_WIDTH_HALF: begin `RV32_MEM_WIDTH_HALF: begin
case (result_in[0]) case (result_in[0])
1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:16]}; 1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:16]};
1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:0]}; 1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:0]};
endcase endcase
end end
RV32_MEM_WIDTH_BYTE: begin `RV32_MEM_WIDTH_BYTE: begin
case (result_in[1:0]) case (result_in[1:0])
2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:24]}; 2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:24]};
2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[23]}}, read_value_in[23:16]}; 2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[23]}}, read_value_in[23:16]};

84
rv32_opcodes.sv
View file

@ -1,56 +1,56 @@
`ifndef RV32_OPCODES `ifndef RV32_OPCODES
`define RV32_OPCODES `define RV32_OPCODES
localparam RV32_OPCODE_LOAD = 7'b0000011; `define RV32_OPCODE_LOAD 7'b0000011
localparam RV32_OPCODE_MISC_MEM = 7'b0001111; `define RV32_OPCODE_MISC_MEM 7'b0001111
localparam RV32_OPCODE_OP_IMM = 7'b0010011; `define RV32_OPCODE_OP_IMM 7'b0010011
localparam RV32_OPCODE_AUIPC = 7'b0010111; `define RV32_OPCODE_AUIPC 7'b0010111
localparam RV32_OPCODE_STORE = 7'b0100011; `define RV32_OPCODE_STORE 7'b0100011
localparam RV32_OPCODE_OP = 7'b0110011; `define RV32_OPCODE_OP 7'b0110011
localparam RV32_OPCODE_LUI = 7'b0110111; `define RV32_OPCODE_LUI 7'b0110111
localparam RV32_OPCODE_BRANCH = 7'b1100011; `define RV32_OPCODE_BRANCH 7'b1100011
localparam RV32_OPCODE_JALR = 7'b1100111; `define RV32_OPCODE_JALR 7'b1100111
localparam RV32_OPCODE_JAL = 7'b1101111; `define RV32_OPCODE_JAL 7'b1101111
localparam RV32_OPCODE_SYSTEM = 7'b1110011; `define RV32_OPCODE_SYSTEM 7'b1110011
localparam RV32_FUNCT3_ANY = 3'b???; `define RV32_FUNCT3_ANY 3'b???
localparam RV32_FUNCT3_ZERO = 3'b000; `define RV32_FUNCT3_ZERO 3'b000
localparam RV32_FUNCT3_BRANCH_BEQ = 3'b000; `define RV32_FUNCT3_BRANCH_BEQ 3'b000
localparam RV32_FUNCT3_BRANCH_BNE = 3'b001; `define RV32_FUNCT3_BRANCH_BNE 3'b001
localparam RV32_FUNCT3_BRANCH_BLT = 3'b100; `define RV32_FUNCT3_BRANCH_BLT 3'b100
localparam RV32_FUNCT3_BRANCH_BGE = 3'b101; `define RV32_FUNCT3_BRANCH_BGE 3'b101
localparam RV32_FUNCT3_BRANCH_BLTU = 3'b110; `define RV32_FUNCT3_BRANCH_BLTU 3'b110
localparam RV32_FUNCT3_BRANCH_BGEU = 3'b111; `define RV32_FUNCT3_BRANCH_BGEU 3'b111
localparam RV32_FUNCT3_LOAD_LB = 3'b000; `define RV32_FUNCT3_LOAD_LB 3'b000
localparam RV32_FUNCT3_LOAD_LH = 3'b001; `define RV32_FUNCT3_LOAD_LH 3'b001
localparam RV32_FUNCT3_LOAD_LW = 3'b010; `define RV32_FUNCT3_LOAD_LW 3'b010
localparam RV32_FUNCT3_LOAD_LBU = 3'b100; `define RV32_FUNCT3_LOAD_LBU 3'b100
localparam RV32_FUNCT3_LOAD_LHU = 3'b101; `define RV32_FUNCT3_LOAD_LHU 3'b101
localparam RV32_FUNCT3_STORE_SB = 3'b000; `define RV32_FUNCT3_STORE_SB 3'b000
localparam RV32_FUNCT3_STORE_SH = 3'b001; `define RV32_FUNCT3_STORE_SH 3'b001
localparam RV32_FUNCT3_STORE_SW = 3'b010; `define RV32_FUNCT3_STORE_SW 3'b010
localparam RV32_FUNCT3_OP_ADD_SUB = 3'b000; `define RV32_FUNCT3_OP_ADD_SUB 3'b000
localparam RV32_FUNCT3_OP_SLL = 3'b001; `define RV32_FUNCT3_OP_SLL 3'b001
localparam RV32_FUNCT3_OP_SLT = 3'b010; `define RV32_FUNCT3_OP_SLT 3'b010
localparam RV32_FUNCT3_OP_SLTU = 3'b011; `define RV32_FUNCT3_OP_SLTU 3'b011
localparam RV32_FUNCT3_OP_XOR = 3'b100; `define RV32_FUNCT3_OP_XOR 3'b100
localparam RV32_FUNCT3_OP_SRL_SRA = 3'b101; `define RV32_FUNCT3_OP_SRL_SRA 3'b101
localparam RV32_FUNCT3_OP_OR = 3'b110; `define RV32_FUNCT3_OP_OR 3'b110
localparam RV32_FUNCT3_OP_AND = 3'b111; `define RV32_FUNCT3_OP_AND 3'b111
localparam RV32_FUNCT3_MISC_MEM_FENCE = 3'b000; `define RV32_FUNCT3_MISC_MEM_FENCE 3'b000
localparam RV32_FUNCT3_MISC_MEM_FENCE_I = 3'b001; `define RV32_FUNCT3_MISC_MEM_FENCE_I 3'b001
localparam RV32_FUNCT7_ANY = 7'b???????; `define RV32_FUNCT7_ANY 7'b???????
localparam RV32_FUNCT7_ZERO = 7'b0000000; `define RV32_FUNCT7_ZERO 7'b0000000
localparam RV32_FUNCT7_OP_SRA = 7'b0100000; `define RV32_FUNCT7_OP_SRA 7'b0100000
localparam RV32_FUNCT7_OP_SUB = 7'b0100000; `define RV32_FUNCT7_OP_SUB 7'b0100000
localparam RV32_INSTR_NOP = {12'bx, 5'b0, 3'bx, 5'b0, RV32_OPCODE_OP_IMM}; `define RV32_INSTR_NOP {12'bx, 5'b0, 3'bx, 5'b0, `RV32_OPCODE_OP_IMM}
`endif `endif

16
uart.sv
View file

@ -1,9 +1,9 @@
`ifndef UART `ifndef UART
`define UART `define UART
localparam UART_REG_CLK_DIV = 2'b00; `define UART_REG_CLK_DIV 2'b00
localparam UART_REG_STATUS = 2'b01; `define UART_REG_STATUS 2'b01
localparam UART_REG_DATA = 2'b10; `define UART_REG_DATA 2'b10
module uart ( module uart (
input clk, input clk,
@ -48,13 +48,13 @@ module uart (
always_comb begin always_comb begin
if (sel_in) begin if (sel_in) begin
case (address_in[3:2]) case (address_in[3:2])
UART_REG_CLK_DIV: begin `UART_REG_CLK_DIV: begin
read_value_out = {16'b0, clk_div}; read_value_out = {16'b0, clk_div};
end end
UART_REG_STATUS: begin `UART_REG_STATUS: begin
read_value_out = {30'b0, rx_read_ready, tx_write_ready}; read_value_out = {30'b0, rx_read_ready, tx_write_ready};
end end
UART_REG_DATA: begin `UART_REG_DATA: begin
read_value_out = {{24{~rx_read_ready}}, rx_read_ready ? rx_read_buf : 8'b0}; read_value_out = {{24{~rx_read_ready}}, rx_read_ready ? rx_read_buf : 8'b0};
end end
default: begin default: begin
@ -69,14 +69,14 @@ module uart (
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (sel_in) begin if (sel_in) begin
case (address_in[3:2]) case (address_in[3:2])
UART_REG_CLK_DIV: begin `UART_REG_CLK_DIV: begin
if (write_mask_in[1]) if (write_mask_in[1])
clk_div[15:8] <= write_value_in[15:8]; clk_div[15:8] <= write_value_in[15:8];
if (write_mask_in[0]) if (write_mask_in[0])
clk_div[7:0] <= write_value_in[7:0]; clk_div[7:0] <= write_value_in[7:0];
end end
UART_REG_DATA: begin `UART_REG_DATA: begin
if (read_in) if (read_in)
rx_read_ready <= 0; rx_read_ready <= 0;