3 commits

Author	SHA1	Message	Date
Graham Edgecombe	22bce1bdeb	Fix compatibility with iverilog ... This commit: * changes the type of all output variables to logic * splits variable declaration and assignment * declares variables before modules that use the variables	2017-12-09 21:03:45 +00:00
Graham Edgecombe	3539f67764	Replace wire with logic	2017-12-07 22:37:58 +00:00
Graham Edgecombe	08c4451abf	Add clock divider	2017-12-07 22:37:58 +00:00