Graham Edgecombe
b4c58919b6
Disable CSR writes if the execute stage is stalled
2018-01-01 19:30:31 +00:00
Graham Edgecombe
2a1ec25a66
Make RV32_ISA_VALUE comment consistent with the opcodes comment
2017-12-31 17:11:56 +00:00
Graham Edgecombe
e9d60ba3e9
Hard-wire pmpcfg and pmpaddr CSRs to 0
2017-12-31 16:55:25 +00:00
Graham Edgecombe
0f094c67db
Hard-wire hpmevent and hpmcounter CSRs to 0
2017-12-31 16:03:11 +00:00
Graham Edgecombe
5011731355
Add mcycle and minstret CSRs
2017-12-31 15:43:06 +00:00
Graham Edgecombe
26ec3542e4
Add mscratch CSR
2017-12-31 11:13:07 +00:00
Graham Edgecombe
73717d320d
Fix CSR write value mux
2017-12-31 11:12:56 +00:00
Graham Edgecombe
63c5585fda
Add misa CSR
2017-12-31 10:36:25 +00:00
Graham Edgecombe
a430c50f16
Add machine information CSRs
2017-12-31 10:29:17 +00:00
Graham Edgecombe
426daa39d6
Replace binary CSR constants with hex
...
This matches the documentation.
2017-12-31 10:15:46 +00:00
Graham Edgecombe
276688f9ef
Move CSR access to the execute stage
...
This reduces the amount of logic slightly, and also removes the one
cycle delay between a CSR read and a subsequent instruction reading from
the destination register.
2017-12-30 11:34:14 +00:00
Graham Edgecombe
3f19fc4226
Replace parallel 32-bit adders with a single 64-bit adder
2017-12-29 17:24:04 +00:00
Graham Edgecombe
21e7ee2b8c
Remove unused stall_in input from rv32_csrs
2017-12-29 16:26:11 +00:00
Graham Edgecombe
63cd024d5c
Fix instret rollover
2017-12-29 16:23:33 +00:00
Graham Edgecombe
4b6218c2a8
Add initial CSR support
2017-12-29 15:29:15 +00:00
