Graham Edgecombe
9b1e27cc0d
Combine the instruction and data buses
2017-12-25 23:33:53 +00:00
Graham Edgecombe
04dc25c5dc
Merge memory bus inputs/outputs in the port list
...
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
2017-12-12 21:15:11 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
0be0da3917
Add memory address decoding
2017-12-07 22:37:58 +00:00
Graham Edgecombe
281009a64c
Increase size of data RAM to 8 KB
2017-12-07 22:37:58 +00:00
Graham Edgecombe
018faac560
Add memory bus and move data memory to a separate module
2017-12-07 22:37:58 +00:00
