Graham Edgecombe
9b1e27cc0d
Combine the instruction and data buses
2017-12-25 23:33:53 +00:00
Graham Edgecombe
58ff5c9ec7
Rename rv32_hazard to rv32_hazard_unit
2017-12-12 21:04:33 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
460159a392
Rename rd_writeback to rd_write
...
This is consistent with the mem_read and mem_write naming.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850
Read mem_{read,write}_en to mem_{read,write}
2017-12-07 22:37:58 +00:00
Graham Edgecombe
cc1f73e19e
Replace pointless if with assign in the hazard unit
2017-12-07 22:37:58 +00:00
Graham Edgecombe
da26f86f25
Remove two cycle load-use stall
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There's no need for it as we forward results from the writeback to the
execute stage.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0c3b91e733
Fix load-use hazard logic
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0acde319b0
Stall the decode stage if it is waiting on a load
2017-12-07 22:37:58 +00:00
Graham Edgecombe
965311c1e5
Add mem_ prefix to the hazard unit's branch_taken input
2017-12-07 22:37:58 +00:00
Graham Edgecombe
9af1107041
Add comments to rv32_hazard.sv
2017-12-07 22:37:58 +00:00
Graham Edgecombe
5ec95c00a2
Flush the decode/execute stages if a branch is taken
2017-12-07 22:37:58 +00:00
Graham Edgecombe
4c2c44e94d
Add initial hazard unit
2017-12-07 22:37:58 +00:00
