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.gitignore
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Port example program to C
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2017-12-15 20:08:55 +00:00 |
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.gitlab-ci.yml
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Add yosys-config --datdir workaround
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2017-12-15 18:35:26 +00:00 |
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bus_arbiter.sv
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Combine the instruction and data buses
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2017-12-25 23:33:53 +00:00 |
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clk_div.sv
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Fix compatibility with iverilog
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2017-12-09 21:03:45 +00:00 |
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ice40hx8k-b-evn.pcf
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Add serial flash, LED and UART pins
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2017-12-01 23:25:06 +00:00 |
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Makefile
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Pass -Os to gcc
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2017-12-29 16:09:19 +00:00 |
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progmem.c
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Add rdcycle demo
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2017-12-29 16:09:41 +00:00 |
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progmem.lds
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Add rodata to the linker script
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2017-12-25 23:42:32 +00:00 |
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ram.sv
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Swap byte order in the ram module
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2017-12-26 14:15:12 +00:00 |
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rv32.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_alu.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_branch.sv
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Split decode stage into smaller modules
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2017-12-27 14:05:09 +00:00 |
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rv32_control.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_csrs.sv
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Remove unused stall_in input from rv32_csrs
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2017-12-29 16:26:11 +00:00 |
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rv32_decode.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_execute.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_fetch.sv
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Combine the instruction and data buses
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2017-12-25 23:33:53 +00:00 |
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rv32_hazard.sv
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Add initial CSR support
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2017-12-29 15:29:15 +00:00 |
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rv32_imm.sv
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Split decode stage into smaller modules
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2017-12-27 14:05:09 +00:00 |
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rv32_mem.sv
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Remove unused stall_in input from rv32_csrs
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2017-12-29 16:26:11 +00:00 |
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rv32_opcodes.sv
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Add MRET and WFI instruction encoding
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2017-12-14 23:46:18 +00:00 |
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rv32_regs.sv
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Fix compatibility with iverilog
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2017-12-09 21:03:45 +00:00 |
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start.s
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Port example program to C
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2017-12-15 20:08:55 +00:00 |
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sync.sv
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Fix compatibility with iverilog
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2017-12-09 21:03:45 +00:00 |
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top.sv
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Combine the instruction and data buses
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2017-12-25 23:33:53 +00:00 |
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top.ys
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Pass -full to opt
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2017-12-08 22:29:22 +00:00 |
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uart.sv
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Merge memory bus inputs/outputs in the port list
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2017-12-12 21:15:11 +00:00 |