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32-bit RISC-V system on chip for iCE40 FPGAs
128 commits 1 branch 0 tags 149 KiB
SystemVerilog 96.1%
Makefile 2.3%
C 0.9%
Assembly 0.4%
Tcl 0.3%
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Graham Edgecombe 276688f9ef Move CSR access to the execute stage 
This reduces the amount of logic slightly, and also removes the one
cycle delay between a CSR read and a subsequent instruction reading from
the destination register.
2017-12-30 11:34:14 +00:00
.gitignore Port example program to C 2017-12-15 20:08:55 +00:00
.gitlab-ci.yml Add yosys-config --datdir workaround 2017-12-15 18:35:26 +00:00
bus_arbiter.sv Combine the instruction and data buses 2017-12-25 23:33:53 +00:00
clk_div.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf Add serial flash, LED and UART pins 2017-12-01 23:25:06 +00:00
Makefile Replace -Os with -O2 2017-12-29 17:18:36 +00:00
progmem.c Replace __asm__ with asm 2017-12-29 17:09:53 +00:00
progmem.lds Add rodata to the linker script 2017-12-25 23:42:32 +00:00
ram.sv Swap byte order in the ram module 2017-12-26 14:15:12 +00:00
rv32.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_alu.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_branch.sv Split decode stage into smaller modules 2017-12-27 14:05:09 +00:00
rv32_control.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_csrs.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_decode.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_execute.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_fetch.sv Combine the instruction and data buses 2017-12-25 23:33:53 +00:00
rv32_hazard.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_imm.sv Split decode stage into smaller modules 2017-12-27 14:05:09 +00:00
rv32_mem.sv Move CSR access to the execute stage 2017-12-30 11:34:14 +00:00
rv32_opcodes.sv Add MRET and WFI instruction encoding 2017-12-14 23:46:18 +00:00
rv32_regs.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
start.s Port example program to C 2017-12-15 20:08:55 +00:00
sync.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
top.sv Combine the instruction and data buses 2017-12-25 23:33:53 +00:00
top.ys Pass -full to opt 2017-12-08 22:29:22 +00:00
uart.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00